Lines Matching full:cpu
2 * riscv TCG cpu class initialization
22 #include "tcg-cpu.h"
23 #include "cpu.h"
33 #include "accel/accel-cpu-target.h"
34 #include "accel/tcg/cpu-ops.h"
73 static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, in riscv_cpu_write_misa_bit() argument
76 CPURISCVState *env = &cpu->env; in riscv_cpu_write_misa_bit()
104 RISCVCPU *cpu = env_archcpu(env); in riscv_get_tb_cpu_state() local
109 if (cpu->cfg.ext_zve32x) { in riscv_get_tb_cpu_state()
122 uint32_t vlmax = vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); in riscv_get_tb_cpu_state()
180 if (cpu->cfg.debug && !icount_enabled()) { in riscv_get_tb_cpu_state()
202 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_cpu_synchronize_from_tb() local
203 CPURISCVState *env = &cpu->env; in riscv_cpu_synchronize_from_tb()
220 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_restore_state_to_opc() local
221 CPURISCVState *env = &cpu->env; in riscv_restore_state_to_opc()
339 static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) in riscv_cpu_enable_named_feat() argument
347 cpu->cfg.cbom_blocksize = 64; in riscv_cpu_enable_named_feat()
348 cpu->cfg.cbop_blocksize = 64; in riscv_cpu_enable_named_feat()
349 cpu->cfg.cboz_blocksize = 64; in riscv_cpu_enable_named_feat()
353 riscv_cpu_write_misa_bit(cpu, RVH, true); in riscv_cpu_enable_named_feat()
357 cpu->cfg.ext_smstateen = true; in riscv_cpu_enable_named_feat()
382 static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, in cpu_cfg_ext_auto_update() argument
385 CPURISCVState *env = &cpu->env; in cpu_cfg_ext_auto_update()
386 bool prev_val = isa_ext_is_enabled(cpu, ext_offset); in cpu_cfg_ext_auto_update()
405 isa_ext_update_enabled(cpu, ext_offset, value); in cpu_cfg_ext_auto_update()
436 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) in riscv_cpu_disable_priv_spec_isa_exts() argument
438 CPURISCVState *env = &cpu->env; in riscv_cpu_disable_priv_spec_isa_exts()
443 if (isa_ext_is_enabled(cpu, edata->ext_enable_offset) && in riscv_cpu_disable_priv_spec_isa_exts()
454 isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); in riscv_cpu_disable_priv_spec_isa_exts()
477 static void riscv_cpu_update_named_features(RISCVCPU *cpu) in riscv_cpu_update_named_features() argument
479 if (cpu->env.priv_ver >= PRIV_VERSION_1_11_0) { in riscv_cpu_update_named_features()
480 cpu->cfg.has_priv_1_11 = true; in riscv_cpu_update_named_features()
483 if (cpu->env.priv_ver >= PRIV_VERSION_1_12_0) { in riscv_cpu_update_named_features()
484 cpu->cfg.has_priv_1_12 = true; in riscv_cpu_update_named_features()
487 if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) { in riscv_cpu_update_named_features()
488 cpu->cfg.has_priv_1_13 = true; in riscv_cpu_update_named_features()
491 cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && in riscv_cpu_update_named_features()
492 cpu->cfg.cbop_blocksize == 64 && in riscv_cpu_update_named_features()
493 cpu->cfg.cboz_blocksize == 64; in riscv_cpu_update_named_features()
495 cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen; in riscv_cpu_update_named_features()
497 cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) && in riscv_cpu_update_named_features()
498 cpu->cfg.ext_ssstateen; in riscv_cpu_update_named_features()
500 cpu->cfg.ext_ziccrse = cpu->cfg.has_priv_1_11; in riscv_cpu_update_named_features()
503 static void riscv_cpu_validate_g(RISCVCPU *cpu) in riscv_cpu_validate_g() argument
512 if (riscv_has_ext(&cpu->env, bit)) { in riscv_cpu_validate_g()
517 riscv_cpu_write_misa_bit(cpu, bit, true); in riscv_cpu_validate_g()
526 if (!cpu->cfg.ext_zicsr) { in riscv_cpu_validate_g()
528 cpu->cfg.ext_zicsr = true; in riscv_cpu_validate_g()
534 if (!cpu->cfg.ext_zifencei) { in riscv_cpu_validate_g()
536 cpu->cfg.ext_zifencei = true; in riscv_cpu_validate_g()
543 static void riscv_cpu_validate_b(RISCVCPU *cpu) in riscv_cpu_validate_b() argument
547 if (!cpu->cfg.ext_zba) { in riscv_cpu_validate_b()
549 cpu->cfg.ext_zba = true; in riscv_cpu_validate_b()
555 if (!cpu->cfg.ext_zbb) { in riscv_cpu_validate_b()
557 cpu->cfg.ext_zbb = true; in riscv_cpu_validate_b()
563 if (!cpu->cfg.ext_zbs) { in riscv_cpu_validate_b()
565 cpu->cfg.ext_zbs = true; in riscv_cpu_validate_b()
574 * cpu->cfg accordingly.
576 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) in riscv_cpu_validate_set_extensions() argument
578 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); in riscv_cpu_validate_set_extensions()
579 CPURISCVState *env = &cpu->env; in riscv_cpu_validate_set_extensions()
583 riscv_cpu_validate_g(cpu); in riscv_cpu_validate_set_extensions()
587 riscv_cpu_validate_b(cpu); in riscv_cpu_validate_set_extensions()
619 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
624 if ((cpu->cfg.ext_zacas) && !riscv_has_ext(env, RVA)) { in riscv_cpu_validate_set_extensions()
629 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { in riscv_cpu_validate_set_extensions()
634 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
639 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
644 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
655 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); in riscv_cpu_validate_set_extensions()
663 if (cpu->cfg.ext_zve64d) { in riscv_cpu_validate_set_extensions()
671 if (cpu->cfg.ext_zve32f) { in riscv_cpu_validate_set_extensions()
678 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { in riscv_cpu_validate_set_extensions()
683 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { in riscv_cpu_validate_set_extensions()
688 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { in riscv_cpu_validate_set_extensions()
693 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { in riscv_cpu_validate_set_extensions()
698 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { in riscv_cpu_validate_set_extensions()
703 if (cpu->cfg.ext_zfinx) { in riscv_cpu_validate_set_extensions()
704 if (!cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
715 if (cpu->cfg.ext_zcmop && !cpu->cfg.ext_zca) { in riscv_cpu_validate_set_extensions()
720 if (mcc->def->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { in riscv_cpu_validate_set_extensions()
725 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { in riscv_cpu_validate_set_extensions()
730 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { in riscv_cpu_validate_set_extensions()
735 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || in riscv_cpu_validate_set_extensions()
736 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { in riscv_cpu_validate_set_extensions()
742 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { in riscv_cpu_validate_set_extensions()
748 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
753 if ((cpu->cfg.ext_zvbb || cpu->cfg.ext_zvkb || cpu->cfg.ext_zvkg || in riscv_cpu_validate_set_extensions()
754 cpu->cfg.ext_zvkned || cpu->cfg.ext_zvknha || cpu->cfg.ext_zvksed || in riscv_cpu_validate_set_extensions()
755 cpu->cfg.ext_zvksh) && !cpu->cfg.ext_zve32x) { in riscv_cpu_validate_set_extensions()
761 if ((cpu->cfg.ext_zvbc || cpu->cfg.ext_zvknhb) && !cpu->cfg.ext_zve64x) { in riscv_cpu_validate_set_extensions()
768 if (cpu->cfg.ext_zicntr && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
773 cpu->cfg.ext_zicntr = false; in riscv_cpu_validate_set_extensions()
776 if (cpu->cfg.ext_zihpm && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
781 cpu->cfg.ext_zihpm = false; in riscv_cpu_validate_set_extensions()
784 if (cpu->cfg.ext_zicfiss) { in riscv_cpu_validate_set_extensions()
785 if (!cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
797 if (!cpu->cfg.ext_zimop) { in riscv_cpu_validate_set_extensions()
801 if (cpu->cfg.ext_zca && !cpu->cfg.ext_zcmop) { in riscv_cpu_validate_set_extensions()
807 if (!cpu->cfg.ext_zihpm) { in riscv_cpu_validate_set_extensions()
808 cpu->cfg.pmu_mask = 0; in riscv_cpu_validate_set_extensions()
809 cpu->pmu_avail_ctrs = 0; in riscv_cpu_validate_set_extensions()
812 if (cpu->cfg.ext_zicfilp && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
817 if (mcc->def->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { in riscv_cpu_validate_set_extensions()
822 if ((cpu->cfg.ext_smctr || cpu->cfg.ext_ssctr) && in riscv_cpu_validate_set_extensions()
823 (!riscv_has_ext(env, RVS) || !cpu->cfg.ext_sscsrind)) { in riscv_cpu_validate_set_extensions()
829 cpu->cfg.ext_smctr = false; in riscv_cpu_validate_set_extensions()
830 cpu->cfg.ext_ssctr = false; in riscv_cpu_validate_set_extensions()
837 riscv_cpu_disable_priv_spec_isa_exts(cpu); in riscv_cpu_validate_set_extensions()
841 static bool riscv_cpu_validate_profile_satp(RISCVCPU *cpu, in riscv_cpu_validate_profile_satp() argument
845 int satp_max = cpu->cfg.max_satp_mode; in riscv_cpu_validate_profile_satp()
850 bool is_32bit = riscv_cpu_is_32bit(cpu); in riscv_cpu_validate_profile_satp()
866 static void riscv_cpu_check_parent_profile(RISCVCPU *cpu, in riscv_cpu_check_parent_profile() argument
878 parent_enabled = object_property_get_bool(OBJECT(cpu), parent_name, NULL); in riscv_cpu_check_parent_profile()
882 static void riscv_cpu_validate_profile(RISCVCPU *cpu, in riscv_cpu_validate_profile() argument
885 CPURISCVState *env = &cpu->env; in riscv_cpu_validate_profile()
893 profile_impl = riscv_cpu_validate_profile_satp(cpu, profile, in riscv_cpu_validate_profile()
917 if (!riscv_has_ext(&cpu->env, bit)) { in riscv_cpu_validate_profile()
930 if (!isa_ext_is_enabled(cpu, ext_offset)) { in riscv_cpu_validate_profile()
942 riscv_cpu_check_parent_profile(cpu, profile, profile->u_parent); in riscv_cpu_validate_profile()
943 riscv_cpu_check_parent_profile(cpu, profile, profile->s_parent); in riscv_cpu_validate_profile()
946 static void riscv_cpu_validate_profiles(RISCVCPU *cpu) in riscv_cpu_validate_profiles() argument
949 riscv_cpu_validate_profile(cpu, riscv_profiles[i]); in riscv_cpu_validate_profiles()
986 static void cpu_enable_implied_rule(RISCVCPU *cpu, in cpu_enable_implied_rule() argument
989 CPURISCVState *env = &cpu->env; in cpu_enable_implied_rule()
995 enabled = test_bit(cpu->env.mhartid, rule->enabled); in cpu_enable_implied_rule()
1017 cpu_enable_implied_rule(cpu, ir); in cpu_enable_implied_rule()
1026 cpu_cfg_ext_auto_update(cpu, rule->implied_multi_exts[i], true); in cpu_enable_implied_rule()
1033 cpu_enable_implied_rule(cpu, ir); in cpu_enable_implied_rule()
1038 bitmap_set(rule->enabled, cpu->env.mhartid, 1); in cpu_enable_implied_rule()
1044 static void cpu_enable_zc_implied_rules(RISCVCPU *cpu) in cpu_enable_zc_implied_rules() argument
1046 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); in cpu_enable_zc_implied_rules()
1047 CPURISCVState *env = &cpu->env; in cpu_enable_zc_implied_rules()
1049 if (cpu->cfg.ext_zce) { in cpu_enable_zc_implied_rules()
1050 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); in cpu_enable_zc_implied_rules()
1051 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true); in cpu_enable_zc_implied_rules()
1052 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true); in cpu_enable_zc_implied_rules()
1053 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true); in cpu_enable_zc_implied_rules()
1056 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); in cpu_enable_zc_implied_rules()
1062 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true); in cpu_enable_zc_implied_rules()
1065 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true); in cpu_enable_zc_implied_rules()
1069 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcd), true); in cpu_enable_zc_implied_rules()
1074 static void riscv_cpu_enable_implied_rules(RISCVCPU *cpu) in riscv_cpu_enable_implied_rules() argument
1080 cpu_enable_zc_implied_rules(cpu); in riscv_cpu_enable_implied_rules()
1084 if (riscv_has_ext(&cpu->env, rule->ext)) { in riscv_cpu_enable_implied_rules()
1085 cpu_enable_implied_rule(cpu, rule); in riscv_cpu_enable_implied_rules()
1091 if (isa_ext_is_enabled(cpu, rule->ext)) { in riscv_cpu_enable_implied_rules()
1092 cpu_enable_implied_rule(cpu, rule); in riscv_cpu_enable_implied_rules()
1097 void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp) in riscv_tcg_cpu_finalize_features() argument
1099 CPURISCVState *env = &cpu->env; in riscv_tcg_cpu_finalize_features()
1103 riscv_cpu_enable_implied_rules(cpu); in riscv_tcg_cpu_finalize_features()
1111 riscv_cpu_update_named_features(cpu); in riscv_tcg_cpu_finalize_features()
1112 riscv_cpu_validate_profiles(cpu); in riscv_tcg_cpu_finalize_features()
1114 if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { in riscv_tcg_cpu_finalize_features()
1123 riscv_cpu_validate_set_extensions(cpu, &local_err); in riscv_tcg_cpu_finalize_features()
1129 if (cpu->cfg.pmu_mask) { in riscv_tcg_cpu_finalize_features()
1130 riscv_pmu_init(cpu, &local_err); in riscv_tcg_cpu_finalize_features()
1136 if (cpu->cfg.ext_sscofpmf) { in riscv_tcg_cpu_finalize_features()
1137 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, in riscv_tcg_cpu_finalize_features()
1138 riscv_pmu_timer_cb, cpu); in riscv_tcg_cpu_finalize_features()
1144 void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu) in riscv_tcg_cpu_finalize_dynamic_decoder() argument
1150 decoder_table[i].guard_func(&cpu->cfg)) { in riscv_tcg_cpu_finalize_dynamic_decoder()
1156 cpu->decoders = dynamic_decoders; in riscv_tcg_cpu_finalize_dynamic_decoder()
1159 bool riscv_cpu_tcg_compatible(RISCVCPU *cpu) in riscv_cpu_tcg_compatible() argument
1161 return object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_CPU_HOST) == NULL; in riscv_cpu_tcg_compatible()
1178 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_tcg_cpu_realize() local
1180 if (!riscv_cpu_tcg_compatible(cpu)) { in riscv_tcg_cpu_realize()
1181 g_autofree char *name = riscv_cpu_get_name(cpu); in riscv_tcg_cpu_realize()
1182 error_setg(errp, "'%s' CPU is not compatible with TCG acceleration", in riscv_tcg_cpu_realize()
1188 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); in riscv_tcg_cpu_realize()
1198 CPURISCVState *env = &cpu->env; in riscv_tcg_cpu_realize()
1200 tcg_cflags_set(CPU(cs), CF_PCREL); in riscv_tcg_cpu_realize()
1202 if (cpu->cfg.ext_sstc) { in riscv_tcg_cpu_realize()
1203 riscv_timer_init(cpu); in riscv_tcg_cpu_realize()
1225 RISCVCPU *cpu = RISCV_CPU(obj); in cpu_set_misa_ext_cfg() local
1226 CPURISCVState *env = &cpu->env; in cpu_set_misa_ext_cfg()
1244 g_autofree char *cpuname = riscv_cpu_get_name(cpu); in cpu_set_misa_ext_cfg()
1245 error_setg(errp, "'%s' CPU does not allow enabling extensions", in cpu_set_misa_ext_cfg()
1259 riscv_cpu_write_misa_bit(cpu, misa_bit, value); in cpu_set_misa_ext_cfg()
1267 RISCVCPU *cpu = RISCV_CPU(obj); in cpu_get_misa_ext_cfg() local
1268 CPURISCVState *env = &cpu->env; in cpu_get_misa_ext_cfg()
1333 RISCVCPU *cpu = RISCV_CPU(obj); in cpu_set_profile() local
1343 if (cpu->env.misa_mxl != MXL_RV64) { in cpu_set_profile()
1367 cpu->env.priv_ver = profile->priv_spec; in cpu_set_profile()
1374 riscv_cpu_is_32bit(cpu)); in cpu_set_profile()
1395 riscv_cpu_write_misa_bit(cpu, bit, profile->enabled); in cpu_set_profile()
1403 riscv_cpu_enable_named_feat(cpu, ext_offset); in cpu_set_profile()
1406 cpu_bump_multi_ext_priv_ver(&cpu->env, ext_offset); in cpu_set_profile()
1410 isa_ext_update_enabled(cpu, ext_offset, profile->enabled); in cpu_set_profile()
1466 RISCVCPU *cpu = RISCV_CPU(obj); in cpu_set_multi_ext_cfg() local
1477 warn_report("CPU property '%s' is deprecated. Please use '%s' instead", in cpu_set_multi_ext_cfg()
1483 prev_val = isa_ext_is_enabled(cpu, multi_ext_cfg->offset); in cpu_set_multi_ext_cfg()
1490 g_autofree char *cpuname = riscv_cpu_get_name(cpu); in cpu_set_multi_ext_cfg()
1491 error_setg(errp, "'%s' CPU does not allow enabling extensions", in cpu_set_multi_ext_cfg()
1497 cpu_bump_multi_ext_priv_ver(&cpu->env, multi_ext_cfg->offset); in cpu_set_multi_ext_cfg()
1500 isa_ext_update_enabled(cpu, multi_ext_cfg->offset, value); in cpu_set_multi_ext_cfg()
1549 * Add CPU properties with user-facing flags.
1572 * The 'max' type CPU will have all possible ratified
1577 RISCVCPU *cpu = RISCV_CPU(obj); in riscv_init_max_cpu_extensions() local
1578 CPURISCVState *env = &cpu->env; in riscv_init_max_cpu_extensions()
1585 isa_ext_update_enabled(cpu, prop->offset, true); in riscv_init_max_cpu_extensions()
1592 cpu->cfg.ext_svade = false; in riscv_init_max_cpu_extensions()
1598 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); in riscv_init_max_cpu_extensions()
1599 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); in riscv_init_max_cpu_extensions()
1600 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); in riscv_init_max_cpu_extensions()
1601 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); in riscv_init_max_cpu_extensions()
1603 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); in riscv_init_max_cpu_extensions()
1604 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); in riscv_init_max_cpu_extensions()
1605 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); in riscv_init_max_cpu_extensions()
1608 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); in riscv_init_max_cpu_extensions()
1615 if (cpu->cfg.ext_smrnmi) { in riscv_init_max_cpu_extensions()
1616 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smrnmi), false); in riscv_init_max_cpu_extensions()
1624 if (cpu->cfg.ext_smdbltrp) { in riscv_init_max_cpu_extensions()
1625 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_smdbltrp), false); in riscv_init_max_cpu_extensions()
1636 RISCVCPU *cpu = RISCV_CPU(cs); in riscv_tcg_cpu_instance_init() local
1637 Object *obj = OBJECT(cpu); in riscv_tcg_cpu_instance_init()