Home
last modified time | relevance | path

Searched full:counter (Results 1 – 25 of 266) sorted by relevance

1234567891011

/qemu/include/hw/timer/
H A Dsse-counter.h2 * Arm SSE Subsystem System Counter
13 * This is a model of the "System counter" which is documented in
22 * Consumers of the system counter's timestamp, such as the SSE
25 * interact with an instance of the System Counter. Generally the
27 * code can set to the appropriate instance of the system counter.
37 #define TYPE_SSE_COUNTER "sse-counter"
71 * @counter: SSECounter
74 * Returns the value of the timestamp counter at the specified
78 uint64_t sse_counter_for_timestamp(SSECounter *counter, uint64_t ns);
82 * @counter: SSECounter
[all …]
H A Dsse-timer.h18 * + QOM property "counter": link property to be set to the
19 * TYPE_SSE_COUNTER timestamp counter device this timer runs off
30 #include "hw/timer/sse-counter.h"
42 SSECounter *counter; member
/qemu/include/hw/
H A Dptimer.h55 * - Starting to run with counter = 0 or setting it to "0" while timer
56 * is running causes a trigger and reloads counter with a limit value.
59 * - Counter value of the running timer is one less than the actual value.
63 * counter = counter value at the moment of change (.i.e. one less).
67 /* Periodic timer counter stays with "0" for a one period before wrapping
71 /* Running periodic timer that has counter = limit = 0 would continuously
75 /* Starting to run with/setting counter to "0" won't trigger immediately,
79 /* Starting to run with/setting counter to "0" won't re-load counter
83 /* Make counter value of the running timer represent the actual value and
88 * Starting to run with a zero counter, or setting the counter to "0" via
[all …]
/qemu/hw/net/fsl_etsec/
H A Dregisters.c161 {0x680, "TR64", "Transmit and receive 64-byte frame counter ", ACC_RW, 0x0000000…
162 {0x684, "TR127", "Transmit and receive 65- to 127-byte frame counter", ACC_RW, 0x0000000…
163 {0x688, "TR255", "Transmit and receive 128- to 255-byte frame counter", ACC_RW, 0x0000000…
164 {0x68C, "TR511", "Transmit and receive 256- to 511-byte frame counter", ACC_RW, 0x0000000…
165 {0x690, "TR1K", "Transmit and receive 512- to 1023-byte frame counter", ACC_RW, 0x0000000…
166 {0x694, "TRMAX", "Transmit and receive 1024- to 1518-byte frame counter", ACC_RW, 0x0000000…
171 {0x69C, "RBYT", "Receive byte counter", ACC_RW, 0x00000000},
172 {0x6A0, "RPKT", "Receive packet counter", ACC_RW, 0x00000000},
173 {0x6A4, "RFCS", "Receive FCS error counter", ACC_RW, 0x00000000},
174 {0x6A8, "RMCA", "Receive multicast packet counter", ACC_RW, 0x00000000},
[all …]
/qemu/hw/usb/
H A Du2f-emulated.c38 /* Counter which sync with a file */
40 /* Emulated device counter */
50 struct synced_counter *counter = (struct synced_counter *)vdev_counter; in counter_increment() local
51 ++counter->value; in counter_increment()
54 if (fseek(counter->fp, 0, SEEK_SET) == -1) { in counter_increment()
57 fprintf(counter->fp, "%u\n", counter->value); in counter_increment()
62 struct synced_counter *counter = (struct synced_counter *)vdev_counter; in counter_read() local
63 return counter->value; in counter_read()
82 char *counter; member
215 struct synced_counter *counter) in u2f_emulated_setup_counter() argument
[all …]
/qemu/hw/timer/
H A Dnrf51_timer.c47 s->counter = (s->counter + ticks) % BIT(bitwidths[s->bitmode]); in update_counter()
57 /* Assumes s->counter is up-to-date */
70 if (s->cc[i] <= s->counter) { in rearm_timer()
72 s->counter + s->cc[i]); in rearm_timer()
74 delta_ns = ticks_to_ns(s, s->cc[i] - s->counter); in rearm_timer()
108 if (s->cc[i] > s->counter) { in timer_expire()
109 cc_remaining[i] = s->cc[i] - s->counter; in timer_expire()
112 s->counter + s->cc[i]; in timer_expire()
125 s->counter = 0; in timer_expire()
144 uint32_t counter = s->counter; in counter_compare() local
[all …]
H A Dsse-counter.c2 * Arm SSE Subsystem System Counter
13 * This is a model of the "System counter" which is documented in
17 * The system counter is a non-stop 64-bit up-counter. It provides
20 * from a clock. Internally to the counter the count is actually
34 #include "hw/timer/sse-counter.h"
50 * Although CNTCR defines interrupt-related bits, the counter doesn't
146 /* Counter is disabled and does not increment */ in sse_counter_for_timestamp()
154 * the underlying 88-bit counter for every tick of the in sse_counter_for_timestamp()
157 * how much the full 88-bit counter has moved on; we then in sse_counter_for_timestamp()
177 * Write one 32-bit half of the counter value; startbit is the in sse_write_cntcv()
[all …]
H A Dslavio_timer.c39 * This is the timer/counter part of chip STP2001 (Slave I/O), also
43 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
111 if (t->limit == 0) { /* free-run system or processor counter */ in slavio_timer_get_out()
154 // read limit (system counter mode) or read most signifying in slavio_timer_mem_readl()
155 // part of counter (user mode) in slavio_timer_mem_readl()
169 // read counter and reached bit (system mode) or read lsbits in slavio_timer_mem_readl()
170 // of counter (user mode) in slavio_timer_mem_readl()
180 // only available in processor counter/timer in slavio_timer_mem_readl()
189 // only available in system counter in slavio_timer_mem_readl()
219 // set user counter MSW, reset counter in slavio_timer_mem_writel()
[all …]
H A Dtrace-events13 slavio_timer_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to u…
14 …mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter"
66 nrf51_timer_set_count(uint8_t timer_id, uint8_t counter_id, uint32_t value) "timer %u counter %u co…
87 sse_counter_control_read(uint64_t offset, uint64_t data, unsigned size) "SSE system counter control…
88 sse_counter_control_write(uint64_t offset, uint64_t data, unsigned size) "SSE system counter contro…
89 sse_counter_status_read(uint64_t offset, uint64_t data, unsigned size) "SSE system counter status f…
90 sse_counter_status_write(uint64_t offset, uint64_t data, unsigned size) "SSE system counter status …
91 sse_counter_reset(void) "SSE system counter: reset"
113 hpet_ram_read_reading_counter(uint8_t reg_off, uint64_t cur_tick) "reading counter + %" PRIu8 " = 0…
121 hpet_ram_write_counter_write_while_enabled(void) "Writing counter while HPET enabled!"
[all …]
H A Dsse-timer.c17 * The timer is based around a simple 64-bit incrementing counter
19 * Counter - CompareValue >= 0.
22 * TimerValue = CompareValue[31:0] - Counter[31:0]
28 * AutoIncrValue = Reload + Counter
30 * Counter - AutoIncrValue >= 0
42 #include "hw/timer/sse-counter.h"
103 return sse_counter_for_timestamp(s->counter, in sse_cntpct()
139 uint64_t expiry = sse_counter_tick_to_time(s->counter, nexttick); in sse_set_timer()
151 * This is also the code path for "counter is not running", in sse_set_timer()
391 /* System counter told us we need to recalculate */ in sse_timer_counter_callback()
[all …]
/qemu/target/riscv/
H A Dpmu.c108 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; in riscv_pmu_incr_ctr_rv32() local
126 if (counter->mhpmcounter_val == max_val) { in riscv_pmu_incr_ctr_rv32()
127 if (counter->mhpmcounterh_val == max_val) { in riscv_pmu_incr_ctr_rv32()
128 counter->mhpmcounter_val = 0; in riscv_pmu_incr_ctr_rv32()
129 counter->mhpmcounterh_val = 0; in riscv_pmu_incr_ctr_rv32()
136 counter->mhpmcounterh_val++; in riscv_pmu_incr_ctr_rv32()
139 counter->mhpmcounter_val++; in riscv_pmu_incr_ctr_rv32()
148 PMUCTRState *counter = &env->pmu_ctrs[ctr_idx]; in riscv_pmu_incr_ctr_rv64() local
167 if (counter->mhpmcounter_val == max_val) { in riscv_pmu_incr_ctr_rv64()
168 counter->mhpmcounter_val = 0; in riscv_pmu_incr_ctr_rv64()
[all …]
/qemu/include/standard-headers/linux/
H A Dvmclock-abi.h6 * counter, etc.) and real time. It is designed to address the problem of
12 * counter will change within the tolerances of its specification (typically
17 * Second, there may be a step change in the value of the counter itself, as
34 * precise relationship of the CPU counter to real time, as calibrated by the
38 * counter being reliable and consistent across CPUs.
43 * actually messes with the apparent counter *period*. A linear smearing
44 * of 1 ms per second would effectively tweak the counter period by 1000PPM
84 * counter is disrupted, for example on live migration. This lets
86 * performed of the counter against external sources (NTP/PTP/etc.).
110 * In particular, a timestamp based on a counter reading taken
[all …]
/qemu/scripts/
H A Du2f-setup-gen.py25 entropy: bytes, counter: int) -> None:
34 counter: The counter value.
51 # Counter
52 with open(f'{dirpath}/counter', 'w') as f:
53 f.write(f'{str(counter)}\n')
144 # Counter
145 counter = 0
148 write_setup_dir(dirpath, privkey_pem, certificate_pem, entropy, counter)
/qemu/tests/qtest/
H A Dsse-timer-test.c29 /* Base of the System Counter control frame */
32 /* SSE counter register offsets in the control frame */
69 * Reset the system counter and the timer between tests. This in reset_counter_and_timer()
81 /* Basic counter functionality test */ in test_counter()
84 /* The counter should start disabled: check that it doesn't move */ in test_counter()
93 /* Check the counter scaling functionality */ in test_counter()
114 /* We must enable the System Counter or the timer won't run. */ in test_timer()
117 /* Timer starts disabled and with a counter of 0 */ in test_timer()
134 /* Check TVAL view of the counter */ in test_timer()
195 * Test that the timer responds correctly to counter in test_timer_scale_change()
[all …]
H A Dcmsdk-apb-watchdog-test.c172 /* Tests the counter is not running after reset. */
188 * The counter should not be running if WDOGCONTROL.INTEN has not been set, in test_watchdog_reset()
195 /* Let the counter run before reset */ in test_watchdog_reset()
210 /* The counter should not be running after reset. */ in test_watchdog_reset()
219 * Tests inten works as the counter enable based on this description:
221 * Enable the interrupt event, WDOGINT. Set HIGH to enable the counter and the
222 * interrupt, or LOW to disable the counter and interrupt. Reloads the counter
242 * Note: the counter should not be running as long as WDOGCONTROL.INTEN is in test_watchdog_inten()
252 /* Set HIGH WDOGCONTROL.INTEN to enable the counter and the interrupt */ in test_watchdog_inten()
258 /* or LOW to disable the counter and interrupt. */ in test_watchdog_inten()
[all …]
/qemu/hw/riscv/
H A Driscv-iommu-hpm.c46 * Counter should not increment if inhibit bit is set. We can't really in riscv_iommu_hpmcycle_read()
48 * counter value to indicate that counter was not incremented. in riscv_iommu_hpmcycle_read()
119 * It's quite possible that event ID has been changed in counter in riscv_iommu_hpm_incr_ctr()
121 * counter for the old event ID. in riscv_iommu_hpm_incr_ctr()
137 * If the transaction does not have a valid process_id, counter in riscv_iommu_hpm_incr_ctr()
139 * has a valid process_id, counter increments if device_id in riscv_iommu_hpm_incr_ctr()
174 /* Timer callback for cycle counter overflow. */
221 * We are using INT64_MAX here instead to UINT64_MAX because cycle counter in hpm_setup_timer()
240 /* Updates the internal cycle counter state when iocntinh:CY is changed. */
255 * Cycle counter is enabled. Just start the timer again and update in riscv_iommu_process_iocntinh_cy()
[all …]
/qemu/docs/devel/
H A Dlockcnt.rst80 A ``QemuLockCnt`` comprises both a counter and a mutex; it has primitives
81 to increment and decrement the counter, and to take and release the
82 mutex. The counter notes how many visits to the data structures are
85 governing the counter/mutex pair then are the following:
88 counter is zero and the mutex is taken.
90 - A new visit cannot be started while the counter is zero and the
104 This could be implemented simply by protecting the counter with the
135 counter to never become zero. For this reason, this technique is
139 them for each modification of the counter. ``QemuLockCnt`` ensures that
140 all modifications of the counter take the lock appropriately, and it
[all …]
/qemu/hw/core/
H A Dptimer.c203 uint64_t counter; in ptimer_get_count() local
212 /* Figure out the current counter value. */ in ptimer_get_count()
216 counter = 0; in ptimer_get_count()
260 counter = rem / div; in ptimer_get_count()
263 /* Before wrapping around, timer should stay with counter = 0 in ptimer_get_count()
267 /* Counter == delta here, check whether it was in ptimer_get_count()
270 if (counter == s->limit + DELTA_ADJUST) { in ptimer_get_count()
273 } else if (counter == s->limit) { in ptimer_get_count()
274 /* Since the counter is rounded down and now != last, in ptimer_get_count()
275 the counter == limit means that delta was adjusted in ptimer_get_count()
[all …]
/qemu/hw/misc/
H A Dmps2-fpgaio.c36 REG32(COUNTER, 0x18)
55 * Update s->counter and s->pscntr to their true current values in resync_counter()
69 * Work out what PSCNTR and COUNTER have moved to. We assume that in resync_counter()
71 * and that COUNTER increments at the same moment. in resync_counter()
84 * COUNTER every tick after that. in resync_counter()
86 s->counter += ticks - s->pscntr; in resync_counter()
101 * and COUNTER is incremented by y / (s->prescale + 1) in resync_counter()
110 s->counter += y / (s->prescale + 1); in resync_counter()
161 r = s->counter; in mps2_fpgaio_read()
236 s->counter = value; in mps2_fpgaio_write()
[all …]
H A Dmos6522.c155 unsigned int counter; in get_counter() local
162 counter = (ti->counter_value - d) & 0xffff; in get_counter()
164 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); in get_counter()
165 counter = (ti->latch - counter) & 0xffff; in get_counter()
168 counter = (ti->counter_value - d) & 0xffff; in get_counter()
170 return counter; in get_counter()
189 unsigned int counter; in get_next_irq_time() local
195 /* current counter value */ in get_next_irq_time()
201 counter = (ti->counter_value - d) & 0xffff; in get_next_irq_time()
203 counter = (d - (ti->counter_value + 1)) % (ti->latch + 2); in get_next_irq_time()
[all …]
H A Dallwinner-cpucfg.c55 REG_CNT64_CTRL = 0x0280, /* 64-bit Counter Control */
56 REG_CNT64_LOW = 0x0284, /* 64-bit Counter Low */
57 REG_CNT64_HIGH = 0x0288, /* 64-bit Counter High */
148 case REG_CNT64_CTRL: /* 64-bit Counter Control */ in allwinner_cpucfg_read()
149 case REG_CNT64_LOW: /* 64-bit Counter Low */ in allwinner_cpucfg_read()
150 case REG_CNT64_HIGH: /* 64-bit Counter High */ in allwinner_cpucfg_read()
204 case REG_CNT64_CTRL: /* 64-bit Counter Control */ in allwinner_cpucfg_write()
205 case REG_CNT64_LOW: /* 64-bit Counter Low */ in allwinner_cpucfg_write()
206 case REG_CNT64_HIGH: /* 64-bit Counter High */ in allwinner_cpucfg_write()
/qemu/tests/unit/
H A Dtest-aio-multithread.c205 static uint32_t counter; variable
213 counter++; in test_multi_co_mutex_entry()
231 counter = 0; in test_multi_co_mutex()
251 g_test_message("%d iterations/second", counter / seconds); in test_multi_co_mutex()
252 g_assert_cmpint(counter, ==, atomic_counter); in test_multi_co_mutex()
340 counter++; in test_multi_fair_mutex_entry()
352 counter = 0; in test_multi_fair_mutex()
372 g_test_message("%d iterations/second", counter / seconds); in test_multi_fair_mutex()
373 g_assert_cmpint(counter, ==, atomic_counter); in test_multi_fair_mutex()
396 counter++; in test_multi_mutex_entry()
[all …]
/qemu/rust/hw/timer/hpet/src/
H A Ddevice.rs60 /// Counter Size (bit 13)
67 /// Main Counter Tick Period (bits 32:63)
128 /// Main Counter Value Register
129 COUNTER = 0xF0, enumerator
205 /// comparator (extended to counter width)
281 /// calculate next value of the general counter that matches the
379 // counter wraps in addition to an interrupt with comparator match. in set_timer()
536 /// Main Counter Value Register
538 counter: BqlCell<u64>, field
545 /// Offset of main counter relative to qemu clock.
[all …]
/qemu/docs/system/devices/
H A Dusb-u2f.rst53 * counter (four bytes value)
78 * ``counter``: counter value
89 * ``counter``
93 …|qemu_system| -usb -device u2f-emulated,cert=$DIR1/$FILE1,priv=$DIR2/$FILE2,counter=$DIR3/$FILE3,e…
/qemu/include/qemu/
H A Dlockcnt.h30 * Initialize lockcnt's counter to zero and prepare its mutex
44 * qemu_lockcnt_inc: increment a QemuLockCnt's counter
66 * qemu_lockcnt_dec: decrement a QemuLockCnt's counter
72 * qemu_lockcnt_dec_and_lock: decrement a QemuLockCnt's counter and
82 * qemu_lockcnt_dec_if_lock: possibly decrement a QemuLockCnt's counter and

1234567891011