hw/riscv/riscv-iommu-hpm.c

46          * Counter should not increment if inhibit bit is set. We can't really  in riscv_iommu_hpmcycle_read()
48          * counter value to indicate that counter was not incremented.  in riscv_iommu_hpmcycle_read()
119          * It's quite possible that event ID has been changed in counter  in riscv_iommu_hpm_incr_ctr()
121          * counter for the old event ID.  in riscv_iommu_hpm_incr_ctr()
137              * If the transaction does not have a valid process_id, counter  in riscv_iommu_hpm_incr_ctr()
139              * has a valid process_id, counter increments if device_id  in riscv_iommu_hpm_incr_ctr()
174 /* Timer callback for cycle counter overflow. */
221      * We are using INT64_MAX here instead to UINT64_MAX because cycle counter  in hpm_setup_timer()
240 /* Updates the internal cycle counter state when iocntinh:CY is changed. */
255          * Cycle counter is enabled. Just start the timer again and update  in riscv_iommu_process_iocntinh_cy()
263          * Cycle counter is disabled. Stop the timer and update the cycle  in riscv_iommu_process_iocntinh_cy()
264          * counter to record the current value which is last programmed  in riscv_iommu_process_iocntinh_cy()
340     /* Update the counter mask if the event is already enabled. */  in update_event_map()