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/qemu/tests/unit/
H A Dtest-smp-parse.c30 * -sockets/cores/threads
36 .has_cores = hc, .cores = c, \
45 .cores = c, \
52 * -sockets/dies/modules/cores/threads
61 .has_cores = he, .cores = e, \
68 * -sockets/clusters/cores/threads
75 .has_cores = hd, .cores = d, \
82 * -drawers/books/sockets/cores/threads
91 .has_cores = he, .cores = e, \
99 * -drawers/books/sockets/dies/clusters/modules/cores/threads
[all …]
/qemu/hw/core/
H A Dmachine-smp.c58 g_string_append_printf(s, " * cores (%u)", ms->smp.cores); in cpu_hierarchy_to_string()
68 * Any missing parameter in "cpus/maxcpus/sockets/cores/threads" will be
71 * In the calculation of omitted sockets/cores/threads: we prefer sockets
72 * over cores over threads before 6.2, while preferring cores over sockets
96 unsigned cores = config->has_cores ? config->cores : 0; in machine_parse_smp_config() local
112 (config->has_cores && config->cores == 0) || in machine_parse_smp_config()
167 cores = cores > 0 ? cores : 1; in machine_parse_smp_config()
173 /* prefer sockets over cores before 6.2 */ in machine_parse_smp_config()
175 cores = cores > 0 ? cores : 1; in machine_parse_smp_config()
179 modules * cores * threads); in machine_parse_smp_config()
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/qemu/tests/qtest/
H A Dcpu-plug-test.c21 unsigned cores; member
38 "-smp 1,sockets=%u,cores=%u,threads=%u,maxcpus=%u", in test_plug_with_device_add()
40 td->sockets, td->cores, td->threads, td->maxcpus); in test_plug_with_device_add()
95 data->cores = 3; in add_pc_test_case()
97 data->maxcpus = data->sockets * data->cores * data->threads; in add_pc_test_case()
100 mname, data->sockets, data->cores, in add_pc_test_case()
121 data->cores = 3; in add_pseries_test_case()
123 data->maxcpus = data->sockets * data->cores * data->threads; in add_pseries_test_case()
126 mname, data->sockets, data->cores, in add_pseries_test_case()
147 data->cores = 3; in add_s390x_test_case()
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/qemu/target/ppc/
H A Dcpu-models.h44 /* PowerPC 405 cores */
69 /* Xilinx cores */
75 /* PowerPC 440 cores */
93 /* Freescale embedded PowerPC cores */
94 /* PowerPC MPC 5xx cores (aka RCPU) */
96 /* PowerPC MPC 8xx cores (aka PowerQUICC) */
98 /* G2 cores (aka PowerQUICC-II) */
120 /* e200 cores */
124 /* e300 cores */
133 /* e500 cores */
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/qemu/docs/system/arm/
H A Draspi.rst10 Cortex-A7 (4 cores), 1 GiB of RAM
12 Cortex-A53 (4 cores), 512 MiB of RAM
14 Cortex-A53 (4 cores), 1 GiB of RAM
16 Cortex-A72 (4 cores), 2 GiB of RAM
H A Dnuvoton.rst7 NPCM8XX series. NPCM7XX series feature one or two Arm Cortex-A9 CPU cores,
8 while NPCM8XX feature 4 Arm Cortex-A35 CPU cores. Both series contain a
14 The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise
19 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
31 The NPCM8xx SoC is the successor of the NPCM7xx SoC. It has 4 Cortex-A35 cores.
H A Dhighbank.rst5 which has four Cortex-A9 cores.
8 which has four Cortex-A15 cores.
/qemu/docs/system/s390x/
H A Dcpu-topology.rst67 -smp cpus=5,drawer=1,books=1,sockets=8,cores=4,maxcpus=32
73 -smp cpus=5,sockets=8,cores=4,maxcpus=32
133 In the following machine we define 8 sockets with 4 cores each.
139 -smp cpus=5,sockets=8,cores=4,maxcpus=32 \
155 As we have 4 cores in a socket, we have 4 CPUs provided
223 For example, here we set the position of the cores 1,2,3 to
224 drawer 1, book 1, socket 2 and cores 0,9 and 14 to drawer 0,
234 -smp cpus=1,sockets=8,cores=4,maxcpus=32 \
/qemu/docs/system/ppc/
H A Dpowernv.rst77 $ qemu-system-ppc64 -m 2G -machine powernv9 -smp 2,cores=2,threads=1 \
114 $ qemu-system-ppc64 -m 2G -machine powernv9 -smp 2,cores=2,threads=1 -accel tcg,thread=single \
149 number of cores. ``-smp 2,cores=1`` will define a machine with 2
150 sockets of 1 core, whereas ``-smp 2,cores=2`` will define a machine
151 with 1 socket of 2 cores. ``-smp 8,cores=2``, 4 sockets of 2 cores.
/qemu/contrib/plugins/
H A Dcache.c98 static int cores; variable
294 caches = g_new(Cache *, cores); in caches_init()
296 for (i = 0; i < cores; i++) { in caches_init()
403 cache_idx = vcpu_index % cores; in vcpu_mem_access()
439 cache_idx = vcpu_index % cores; in vcpu_insn_exec()
527 for (i = 0; i < cores; i++) { in caches_free()
565 g_assert(cores > 1); in sum_stats()
566 for (i = 0; i < cores; i++) { in sum_stats()
618 for (i = 0; i < cores; i++) { in log_stats()
629 if (cores > 1) { in log_stats()
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/qemu/include/hw/s390x/
H A Dcpu-topology.h68 return (n / smp->cores) % smp->sockets; in s390_std_socket()
73 return (n / (smp->cores * smp->sockets)) % smp->books; in s390_std_book()
78 return (n / (smp->cores * smp->sockets * smp->books)) % smp->drawers; in s390_std_drawer()
/qemu/hw/s390x/
H A Dcpu-topology.c31 * .cores_per_socket: tracks information on the count of cores
83 * Allocate an array to keep the count of cores per socket.
172 * topology by filling the cores starting from the first socket
343 if (s390_topology.cores_per_socket[entry] >= ms->smp.cores) { in s390_topology_setup_cpu()
348 /* Update the count of cores in sockets */ in s390_topology_setup_cpu()
415 ms->smp.cores) { in s390_change_topology()
419 /* Update the count of cores in sockets */ in s390_change_topology()
/qemu/hw/ppc/
H A Dpnv.c88 * 4 * 4 sockets * 12 cores * 8 threads = 1536
133 * The PowerNV cores (and threads) need to use real HW ids and not an
136 * device tree, used in XSCOM to address cores and in interrupt
351 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power8_dt_populate()
408 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power9_dt_populate()
417 i++; /* Big-core groups two QEMU cores */ in pnv_chip_power9_dt_populate()
473 PnvCore *pnv_core = chip->cores[i]; in pnv_chip_power10_dt_populate()
482 i++; /* Big-core groups two QEMU cores */ in pnv_chip_power10_dt_populate()
1079 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); in pnv_init()
1104 * device-tree and TCG SMT code make the 2 cores appear as one big core in pnv_init()
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/qemu/docs/specs/
H A Drapl-msr.rst93 package has 4 cores, 400 ticks maximum can be scheduled on all the cores
108 A 4 cores package can schedule a maximum of 400 ticks per second with 100 ticks
/qemu/target/xtensa/
H A Dimport_core.sh69 grep -qxf core-${NAME}.c "$BASE"/cores.list || \
70 echo core-${NAME}.c >> "$BASE"/cores.list
H A Dmeson.build3 xtensa_cores = fs.read('cores.list')
/qemu/docs/system/riscv/
H A Dsifive_u.rst13 * Up to 4 U54 / U34 cores
31 With QEMU, one can create a machine with 1 E51 core and up to 4 U54 cores. It
33 that the RISC-V cores are replaced by the 32-bit ones (E31 and U34), to help
309 U-Boot proper. Hence the number of cores and size of memory have to match
310 the real hardware, ie: 5 cores (-smp 5) and 8 GiB memory (-m 8G).
H A Dmicrochip-icicle-kit.rst5 SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
19 * 4 U54 cores
/qemu/include/hw/intc/
H A Darm_gic.h35 * + sysbus IRQs: (in order; number will vary depending on number of cores)
51 * whether virtualization extensions are present and on number of cores)
/qemu/tests/functional/
H A Dtest_s390x_topology.py22 the cores, sockets, books and drawers and 2 modifiers attributes,
125 '13,drawers=2,books=2,sockets=3,cores=2,maxcpus=24')
150 '1,drawers=2,books=2,sockets=3,cores=2,maxcpus=24')
168 '1,drawers=2,books=2,sockets=3,cores=2,maxcpus=24')
331 '3,drawers=2,books=2,sockets=3,cores=2,maxcpus=24')
/qemu/include/hw/ppc/
H A Dpnv_chip.h36 PnvCore **cores; member
104 * A SMT8 fused core is a pair of SMT4 cores.
/qemu/hw/loongarch/
H A Dvirt.c828 topo->socket_id = index / (ms->smp.cores * ms->smp.threads); in virt_get_topo_from_index()
829 topo->core_id = index / ms->smp.threads % ms->smp.cores; in virt_get_topo_from_index()
850 int arch_id, threads, cores, sockets; in virt_get_arch_id_from_topo() local
853 cores = topo_align_up(ms->smp.cores); in virt_get_arch_id_from_topo()
855 if ((threads * cores * sockets) > 256) { in virt_get_arch_id_from_topo()
856 error_report("Exceeding max cpuid 256 with sockets[%d] cores[%d]" in virt_get_arch_id_from_topo()
857 " threads[%d]", ms->smp.sockets, ms->smp.cores, in virt_get_arch_id_from_topo()
863 arch_id += topo->socket_id * threads * cores; in virt_get_arch_id_from_topo()
912 if ((cpu->core_id < 0) || (cpu->core_id >= ms->smp.cores)) { in virt_cpu_pre_plug()
915 cpu->core_id, ms->smp.cores - 1); in virt_cpu_pre_plug()
/qemu/include/hw/arm/
H A Dallwinner-h3.h22 * processor cores. Features and specifications include DDR2/DDR3 memory,
103 /** Total number of CPU cores in the H3 SoC */
/qemu/hw/alpha/
H A Dalpha_sys.h1 /* Alpha cores and system support chips. */
/qemu/target/s390x/kvm/
H A Dstsi-topology.c146 sysib->mag[S390_TOPOLOGY_MAG1] = current_machine->smp.cores; in setup_stsi()
152 sysib->mag[S390_TOPOLOGY_MAG1] = current_machine->smp.cores; in setup_stsi()
158 sysib->mag[S390_TOPOLOGY_MAG1] = current_machine->smp.cores; in setup_stsi()

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