Merge tag 'pull-target-arm-20250616' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
* hw/arm/virt: Check bypass iommu is not set for iommu-map DT property
* test

Merge tag 'pull-target-arm-20250616' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
* hw/arm/virt: Check bypass iommu is not set for iommu-map DT property
* tests/functional: Add a test for the realview-eb-mpcore machine
* qemu-options.hx: Fix reversed description of icount sleep behavior
* target/arm: Define raw write for PMU CLR registers
* docs/interop: convert qed_spec.txt to reStructuredText format
* hw/arm: make cpu targeted by arm_load_kernel the primary CPU.
* hw/intc/arm_gic: introduce a first-cpu-index property
* hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions
* linux-user/arm: Fix return value of SYS_cacheflush

# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmhQJLgZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3k+8EACPyIt6Tie/0kuTXG85r06P
# Iqlp59ENb4HNB43bOBlLqNNJydx1GplKnDeDVsz4MyjhtFTZ3xvY+52IbDOgb3YL
# 66uJfu1VgdnYoKOpfi3hEr9PM9QxNkENF/3+Fokn+X5tHzhNY4eo/RREQfz2tKJ5
# aKKvzmcZNYwqFLn8TKCNaAfjmqrdwVpuF+rt//4hGULZGwatt8qmlsXWLstozTAz
# SPx0utJfvblHj6a+49e0lXaL+xU5yho2J01OiNHrIGtED5Oq2Wmj/q0SV3qPiLDH
# hchuDXT71shE2JYoVeINaQpjRWzQNSPXvnEl9SyJ3Ghzop3sOZqE2iPVslvO0l5R
# rfrbR2rLnGcRPOwgntGnSMHiW+DH9ldhMUp7UvhlU3/5MJmWX2jpDfZJPsmmdyFH
# Evrf64yMO7JlLMQSMkTISZampz8aUgdlgrmQDJ4kGpdkp3GWqLE93eQGHCU16k2j
# PzjGxCIeOED4HEeGG3GrPTf0P1dy8WKla2z8ou2ANLqofrKpwFHTuGRl77ETn/bD
# 8c11hdS+uJ4Sx/efVPXWQhjCPNwLJL+DlCW0kKbGfTmiBdlcPPzPbrzmPNinVzJs
# luSGFzNit7Invfn0KZhy3l0iucMWGPdMDqN0B15RA5fFssdkuxZga5H2kOqCswOe
# 3hHo1s5PUbg+x1JAvQvi5g==
# =9lWk
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 16 Jun 2025 10:05:44 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20250616' of https://git.linaro.org/people/pmaydell/qemu-arm:
linux-user/arm: Fix return value of SYS_cacheflush
hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions
hw/intc/arm_gic: introduce a first-cpu-index property
hw/arm: make cpu targeted by arm_load_kernel the primary CPU.
docs/interop: convert qed_spec.txt to reStructuredText format
target/arm: Define raw write for PMU CLR registers
qemu-options.hx: Fix reversed description of icount sleep behavior
tests/functional: Add a test for the realview-eb-mpcore machine
hw/arm/virt: Check bypass iommu is not set for iommu-map DT property

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

show more ...

hw/intc/arm_gic: introduce a first-cpu-index property

This introduces a first-cpu-index property to the arm-gic, as some SOCs
could have two separate GIC (ie: the zynqmp).

Signed-off-by: Clément Ch

hw/intc/arm_gic: introduce a first-cpu-index property

This introduces a first-cpu-index property to the arm-gic, as some SOCs
could have two separate GIC (ie: the zynqmp).

Signed-off-by: Clément Chigot <chigot@adacore.com>
Message-id: 20250526085523.809003-3-chigot@adacore.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: slightly expanded comment documenting GIC property]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Merge tag 'accel-20230628' of https://github.com/philmd/qemu into staging

Accelerators patches

- MAINTAINERS: Update Roman Bolshakov email address
- HAX: Fix a memory leak
- HAX/NVMM/WHPX/HVF: Rena

Merge tag 'accel-20230628' of https://github.com/philmd/qemu into staging

Accelerators patches

- MAINTAINERS: Update Roman Bolshakov email address
- HAX: Fix a memory leak
- HAX/NVMM/WHPX/HVF: Rename per-accel state as AccelCPUState
- KVM: Restrict specific fields from ArchCPU
- WHPX: Re-enable cross-build gitlab-ci job on case sensitive filesystems
- WHPX: Fix error message when setting ProcessorCount fails
- exec/memory: Add definitions for memory listener priorities

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmScVtkACgkQ4+MsLN6t
# wN7p8A//RXuX9gLFT35zx+5axocU3/XBbCsQWSvzzkYoXxmC/TLxvivO66NPGMc0
# C76b1FJUoLS/u9SyJUeIeYkL0rjkzARUKcRpiJXM21WM6ou8Nkz0kuI4ouowt+4K
# i/4chTjxlN5/4PKlHHcX9ZUJ9acVj01zO1BCuj/bVsxO6WMT1kjL+kplVxxFR3aW
# tlbYtUT3v4xmp94FfE2Q9lR25z4usrGnmz2rchaadlVc43kmsNcQRx+EoUdi148n
# lkViRR90sacYPX586s2yxhPpUdtrXjJmEdX0X00urdPqljkRxekHtyTqG4CRZi+K
# hG5NztK7p37GNNXZroL0gpHyr9IX6hZ3o8rmN3IiCOGU6BgQBRUhvvG2sblwcJ1A
# SSiBK4RWtgyIGWt4U6PgVj8IAu55JuqT5xR2r34fH/zccxXlp/B13vadGs7TUK15
# oHDUT4GnKL2R29lVFTl95BzsxwaMtbB9w01CLJk8va2T/97eqtFgvJyuVC9vZb0N
# 41u2RkinaQZ+hbq9TP1G21zpG0eyucEMIQ6loUd7+G3KJFjFfB4JzE2VDm0Y/OVy
# 77cEEQ67wts29fMNSqqPIQCMttDrNj7JqMMknGBQS2iHPgF+B3KjwIjnRaMBt73I
# CKPITOJPmb+kvIUsK3KlONdicEG57cBxFBTZW5+P9pJXF5izrAY=
# =b9hj
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 28 Jun 2023 05:50:49 PM CEST
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]

* tag 'accel-20230628' of https://github.com/philmd/qemu: (30 commits)
exec/memory: Add symbol for the min value of memory listener priority
exec/memory: Add symbol for memory listener priority for device backend
exec/memory: Add symbolic value for memory listener priority for accel
target/i386/WHPX: Fix error message when fail to set ProcessorCount
target/riscv: Restrict KVM-specific fields from ArchCPU
target/ppc: Restrict KVM-specific fields from ArchCPU
target/arm: Restrict KVM-specific fields from ArchCPU
hw/arm/sbsa-ref: Include missing 'sysemu/kvm.h' header
hw/intc/arm_gic: Rename 'first_cpu' argument
hw/intc/arm_gic: Un-inline GIC*/ITS class_name() helpers
accel/kvm: Declare kvm_direct_msi_allowed in stubs
accel/kvm: Re-include "exec/memattrs.h" header
accel: Rename HVF 'struct hvf_vcpu_state' -> AccelCPUState
accel: Rename 'cpu_state' -> 'cs'
accel: Inline WHPX get_whpx_vcpu()
accel: Rename WHPX 'struct whpx_vcpu' -> AccelCPUState
accel: Remove WHPX unreachable error path
accel: Inline NVMM get_qemu_vcpu()
accel: Rename NVMM 'struct qemu_vcpu' -> AccelCPUState
accel: Remove NVMM unreachable error path
...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

hw/intc/arm_gic: Un-inline GIC*/ITS class_name() helpers

"kvm_arm.h" contains external and internal prototype declarations.
Files under the hw/ directory should only access the KVM external
API.

In

hw/intc/arm_gic: Un-inline GIC*/ITS class_name() helpers

"kvm_arm.h" contains external and internal prototype declarations.
Files under the hw/ directory should only access the KVM external
API.

In order to avoid machine / device models to include "kvm_arm.h"
simply to get the QOM GIC/ITS class name, un-inline each class
name getter to the proper device model file.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230405160454.97436-4-philmd@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging

QOM boilerplate cleanup

Documentation build fix:
* memory: Remove kernel-doc comment marker (Eduardo Habk

Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging

QOM boilerplate cleanup

Documentation build fix:
* memory: Remove kernel-doc comment marker (Eduardo Habkost)

QOM cleanups:
* Rename QOM macros for consistency between
TYPE_* and type checking constants (Eduardo Habkost)

QOM new macros:
* OBJECT_DECLARE_* and OBJECT_DEFINE_* macros (Daniel P. Berrangé)
* DECLARE_*_CHECKER macros (Eduardo Habkost)

Automated QOM boilerplate changes:
* Automated changes to use DECLARE_*_CHECKER (Eduardo Habkost
* Automated changes to use OBJECT_DECLARE* (Eduardo Habkost)

# gpg: Signature made Thu 10 Sep 2020 19:17:49 BST
# gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg: issuer "ehabkost@redhat.com"
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/machine-next-pull-request: (33 commits)
virtio-vga: Use typedef name for instance_size
vhost-user-vga: Use typedef name for instance_size
xilinx_axienet: Use typedef name for instance_size
lpc_ich9: Use typedef name for instance_size
omap_intc: Use typedef name for instance_size
xilinx_axidma: Use typedef name for instance_size
tusb6010: Rename TUSB to TUSB6010
pc87312: Rename TYPE_PC87312_SUPERIO to TYPE_PC87312
vfio: Rename PCI_VFIO to VFIO_PCI
usb: Rename USB_SERIAL_DEV to USB_SERIAL
sabre: Rename SABRE_DEVICE to SABRE
rs6000_mc: Rename RS6000MC_DEVICE to RS6000MC
filter-rewriter: Rename FILTER_COLO_REWRITER to FILTER_REWRITER
esp: Rename ESP_STATE to ESP
ahci: Rename ICH_AHCI to ICH9_AHCI
vmgenid: Rename VMGENID_DEVICE to TYPE_VMGENID
vfio: Rename VFIO_AP_DEVICE_TYPE to TYPE_VFIO_AP_DEVICE
dev-smartcard-reader: Rename CCID_DEV_NAME to TYPE_USB_CCID_DEV
ap-device: Rename AP_DEVICE_TYPE to TYPE_AP_DEVICE
gpex: Fix type checking function name
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Use DECLARE_*CHECKER* when possible (--force mode)

Separate run of the TypeCheckMacro converter using the --force
flag, for the cases where typedefs weren't found in the same
header nor in typedefs.

Use DECLARE_*CHECKER* when possible (--force mode)

Separate run of the TypeCheckMacro converter using the --force
flag, for the cases where typedefs weren't found in the same
header nor in typedefs.h.

Generated initially using:

$ ./scripts/codeconverter/converter.py --force -i \
--pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]')

Then each case was manually reviewed, and a comment was added
indicating what's unusual about those type checking
macros/functions. Despite not following the usual pattern, the
changes in this patch were found to be safe.

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20200831210740.126168-15-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>

show more ...

Move QOM typedefs and add missing includes

Some typedefs and macros are defined after the type check macros.
This makes it difficult to automatically replace their
definitions with OBJECT_DECLARE_TY

Move QOM typedefs and add missing includes

Some typedefs and macros are defined after the type check macros.
This makes it difficult to automatically replace their
definitions with OBJECT_DECLARE_TYPE.

Patch generated using:

$ ./scripts/codeconverter/converter.py -i \
--pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]')

which will split "typdef struct { ... } TypedefName"
declarations.

Followed by:

$ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \
$(git grep -l '' -- '*.[ch]')

which will:
- move the typedefs and #defines above the type check macros
- add missing #include "qom/object.h" lines if necessary

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-9-ehabkost@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Message-Id: <20200831210740.126168-10-ehabkost@redhat.com>
Message-Id: <20200831210740.126168-11-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>

show more ...

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200228' into staging

target-arm queue:
* hw/arm: Use TYPE_PL011 to create serial port
* target/arm: Set ID_MMFR4.HPDS for aarc

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200228' into staging

target-arm queue:
* hw/arm: Use TYPE_PL011 to create serial port
* target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn
* hw/arm/integratorcp: Map the audio codec controller
* GICv2: Correctly implement the limited number of priority bits
* target/arm: refactoring of VFP related feature checks and decode
* xilinx_zynq: Fix USB port instantiation
* acceptance tests for n800, n810, integratorcp
* Implement v8.3-RCPC, v8.4-RCPC, v8.3-CCIDX
* arm_gic_kvm: Don't assume kernel can provide a GICv2
(provide better error message for user error)

# gpg: Signature made Fri 28 Feb 2020 16:38:04 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200228: (33 commits)
hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2
target/arm: Implement ARMv8.3-CCIDX
target/arm: Implement v8.4-RCPC
target/arm: Implement v8.3-RCPC
target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0
tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer
tests/acceptance: Extract boot_integratorcp() from test_integratorcp()
tests/acceptance: Add a test for the integratorcp arm machine
tests/acceptance: Add a test for the N800 and N810 arm machines
hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class
hw/arm/xilinx_zynq: Fix USB port instantiation
target/arm: Split VMINMAXNM decode
target/arm: Split VFM decode
target/arm: Add formats for some vfp 2 and 3-register insns
target/arm: Remove ARM_FEATURE_VFP*
linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP
target/arm: Move the vfp decodetree calls next to the base isa
target/arm: Move VLLDM and VLSTM to vfp.decode
target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn
target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

arm_gic: Mask the un-supported priority bits

The GICv2 allows the implementation to implement a variable number
of priority bits; unimplemented bits in the priority registers
are read as zeros, writ

arm_gic: Mask the un-supported priority bits

The GICv2 allows the implementation to implement a variable number
of priority bits; unimplemented bits in the priority registers
are read as zeros, writes ignored. We were previously always
implementing a full 8 bits of priority, which is allowed but not
what the real hardware typically does (which is usually to have
4 or 5 bits of priority).

Add a new device property to allow the number of implemented
property bits to be specified.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Message-id: 1582537164-764-2-git-send-email-sai.pavan.boddu@xilinx.com
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: improved commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180925-1' into staging

target-arm queue:
* target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs
* hw/arm/exynos4210: fix Ex

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180925-1' into staging

target-arm queue:
* target/arm: Fix cpu_get_tb_cpu_state() for non-SVE CPUs
* hw/arm/exynos4210: fix Exynos4210 UART support
* hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes
* arm: Add BBC micro:bit machine
* aspeed/i2c: Fix interrupt handling bugs
* hw/arm/smmu-common: Fix the name of the iommu memory regions
* hw/arm/smmuv3: fix eventq recording and IRQ triggerring
* hw/intc/arm_gic: Document QEMU interface
* hw/intc/arm_gic: Drop GIC_BASE_IRQ macro
* hw/net/pcnet-pci: Convert away from old_mmio accessors
* hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements
* aspeed/timer: fix compile breakage with clang 3.4.2
* hw/arm/aspeed: change the FMC flash model of the AST2500 evb
* hw/arm/aspeed: Minor code cleanups
* target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode

# gpg: Signature made Tue 25 Sep 2018 15:23:11 BST
# gpg: using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20180925-1: (21 commits)
target/arm: Start AArch32 CPUs with EL2 but not EL3 in Hyp mode
aspeed/smc: fix some alignment issues
hw/arm/aspeed: Add an Aspeed machine class
hw/arm/aspeed: change the FMC flash model of the AST2500 evb
aspeed/timer: fix compile breakage with clang 3.4.2
hw/timer/cmsdk-apb-dualtimer: Add missing 'break' statements
hw/net/pcnet-pci: Unify pcnet_ioport_read/write and pcnet_mmio_read/write
hw/net/pcnet-pci: Convert away from old_mmio accessors
hw/intc/arm_gic: Drop GIC_BASE_IRQ macro
hw/intc/arm_gic: Document QEMU interface
hw/arm/smmuv3: fix eventq recording and IRQ triggerring
hw/arm/smmu-common: Fix the name of the iommu memory regions
aspeed/i2c: Fix receive done interrupt handling
aspeed/i2c: Handle receive command in separate function
aspeed/i2c: interrupts should be cleared by software only
arm: Add BBC micro:bit machine
arm: Add Nordic Semiconductor nRF51 SoC
MAINTAINERS: Add NRF51 entry
hw/arm/virt-acpi-build: Add a check for memory-less NUMA nodes
hw/arm/exynos4210: fix Exynos4210 UART support
...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

hw/intc/arm_gic: Document QEMU interface

The GICv2's QEMU interface (sysbus MMIO regions, IRQs,
etc) is now quite complicated with the addition of the
virtualization extensions. Add a comment in the

hw/intc/arm_gic: Document QEMU interface

The GICv2's QEMU interface (sysbus MMIO regions, IRQs,
etc) is now quite complicated with the addition of the
virtualization extensions. Add a comment in the header
file which documents it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20180823103818.31189-1-peter.maydell@linaro.org

show more ...

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160714' into staging

target-arm queue:
* add virtio-mmio transport base address to device path
(avoid an assertion failure w

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160714' into staging

target-arm queue:
* add virtio-mmio transport base address to device path
(avoid an assertion failure with multiple virtio-scsi-devices)
* revert hw/ptimer commit 5a50307 which causes regressions on
SPARC guests
* use Neon to accelerate zero-page checking on AArch64 hosts
* set the MPIDR for TCG to match how KVM does it (and fit with
GICv2/GICv3 restrictions on SGI target lists)
* add some missing AArch32 TLBI hypervisor TLB operations
* m25p80: Fix QIOR/DIOR handling for Winbond
* hw/misc: fix typo in Aspeed SCU hw-strap2 property name
* ast2400: pretend DMAs are done for U-boot
* ast2400: some minor code cleanups

# gpg: Signature made Thu 14 Jul 2016 17:21:30 BST
# gpg: using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg: aka "Peter Maydell <pmaydell@gmail.com>"
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20160714:
ast2400: externalize revision numbers
ast2400: pretend DMAs are done for U-boot
ast2400: replace aspeed_smc_is_implemented()
hw/misc: fix typo in Aspeed SCU hw-strap2 property name
m25p80: Fix QIOR/DIOR handling for Winbond
target-arm: Add missed AArch32 TLBI sytem registers
hw/arm/virt: tcg: adjust MPIDR like KVM
gic: provide defines for v2/v3 targetlist sizes
target-arm: Use Neon for zero checking
Revert "hw/ptimer: Perform counter wrap around if timer already expired"
virtio-mmio: format transport base address in BusClass.get_dev_path

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

gic: provide defines for v2/v3 targetlist sizes

Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 1467378129-23302-2-git-send-email-drjones@redhat.com
Reviewed-by: Peter Maydell <peter.ma

gic: provide defines for v2/v3 targetlist sizes

Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 1467378129-23302-2-git-send-email-drjones@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

show more ...

Merge remote-tracking branch 'afaerber/tags/qom-devices-for-anthony' into staging

QOM device refactorings

* QTest coverage for all machines
* QOM realize for Milkymist UART
* QOM realize for ARM MP

Merge remote-tracking branch 'afaerber/tags/qom-devices-for-anthony' into staging

QOM device refactorings

* QTest coverage for all machines
* QOM realize for Milkymist UART
* QOM realize for ARM MPCore
* device_add bug fixes and cleanups
* QOM for PCMCIA/MicroDrive (last legacy IDE device)

# gpg: Signature made Tue 05 Nov 2013 09:07:03 AM PST using RSA key ID 3E7E013F
# gpg: Can't check signature: public key not found

# By Andreas Färber (49) and others
# Via Andreas Färber
* afaerber/tags/qom-devices-for-anthony: (54 commits)
pcmcia/pxa2xx: QOM'ify PXA2xxPCMCIAState
ide: Drop ide_init2_with_non_qdev_drives()
microdrive: Coding Style cleanups
pcmcia: QOM'ify PCMCIACardState and MicroDriveState
pxa: Fix typo "dettach"
qom: Fix pointer to int property helpers' documentation
qdev-monitor: Inline qdev_init() for device_add
qdev-monitor: Avoid qdev as variable name
qdev: Drop misleading qdev_free() function
qdev-monitor: Unref device when device_add fails
qdev-monitor: Fix crash when device_add is called with abstract driver
qdev-monitor: Clean up qdev_device_add() variable naming
arm11mpcore: Split off RealView MPCore
arm11mpcore: Prepare for QOM embedding
arm11mpcore: Convert mpcore_rirq_state to QOM realize
realview_gic: Prepare for QOM embedding
realview_gic: Convert to QOM realize
arm11mpcore: Convert ARM11MPCorePriveState to QOM realize
arm11mpcore: Split off SCU device
arm11mpcore: Create container MemoryRegion in instance_init
...

show more ...

arm_gic: Extract headers hw/intc/arm_gic{,_common}.h

Rename NCPU to GIC_NCPU and move GICState away from gic_internal.h.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas

arm_gic: Extract headers hw/intc/arm_gic{,_common}.h

Rename NCPU to GIC_NCPU and move GICState away from gic_internal.h.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>

show more ...