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/linux-5.10/arch/arm/boot/dts/
Dkeystone-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for Keystone 2 clock tree
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
18 bit-shift = <23>;
19 bit-mask = <1>;
20 clock-output-names = "mainmuxclk";
[all …]
Dkeystone-k2hk-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 Kepler/Hawking SoC clock nodes
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
10 #clock-cells = <0>;
11 compatible = "ti,keystone,pll-clock";
13 clock-output-names = "arm-pll-clk";
15 reg-names = "control";
19 #clock-cells = <0>;
20 compatible = "ti,keystone,main-pll-clock";
23 reg-names = "control", "multiplier", "post-divider";
[all …]
Dkeystone-k2l-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 lamarr SoC clock nodes
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
10 #clock-cells = <0>;
11 compatible = "ti,keystone,pll-clock";
13 clock-output-names = "arm-pll-clk";
15 reg-names = "control";
19 #clock-cells = <0>;
20 compatible = "ti,keystone,main-pll-clock";
23 reg-names = "control", "multiplier", "post-divider";
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Dkeystone-k2e-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
10 #clock-cells = <0>;
11 compatible = "ti,keystone,main-pll-clock";
14 reg-names = "control", "multiplier", "post-divider";
18 #clock-cells = <0>;
19 compatible = "ti,keystone,pll-clock";
21 clock-output-names = "papllclk";
23 reg-names = "control";
27 #clock-cells = <0>;
[all …]
Ddm814x-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
10 #clock-cells = <1>;
11 compatible = "ti,dm814-adpll-s-clock";
14 clock-names = "clkinp", "clkinpulow", "clkinphif";
15 clock-output-names = "481c5040.adpll.dcoclkldo",
22 #clock-cells = <1>;
23 compatible = "ti,dm814-adpll-lj-clock";
26 clock-names = "clkinp", "clkinpulow";
27 clock-output-names = "481c5080.adpll.dcoclkldo",
33 #clock-cells = <1>;
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Dstih418-clock.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/stih418-clks.h>
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
14 clock-output-names = "CLK_SYSIN";
17 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
[all …]
Dstih410-clock.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/stih410-clks.h>
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
14 clock-output-names = "CLK_SYSIN";
17 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
[all …]
Dstih407-clock.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/stih407-clks.h>
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
16 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <0>;
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/linux-5.10/Documentation/devicetree/bindings/clock/
Dclock-bindings.txt1 This binding is a work-in-progress, and are based on some experimental
4 Sources of clock signal can be represented by any node in the device
5 tree. Those nodes are designated as clock providers. Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
7 outputs to clock inputs. Similar to the gpio specifiers, a clock
8 specifier is an array of zero, one or more cells identifying the clock
9 output on a device. The length of a clock specifier is defined by the
10 value of a #clock-cells property in the clock provider node.
14 ==Clock providers==
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
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Dallwinner,sun4i-a10-usb-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-usb-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 USB Clock Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
19 The additional ID argument passed to the clock shall refer to
20 the index of the output.
[all …]
Dxgene.txt1 Device Tree Clock bindings for APM X-Gene
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
11 "apm,xgene-pmd-clock" - for a X-Gene PMD clock
12 "apm,xgene-device-clock" - for a X-Gene device clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
[all …]
Dnuvoton,npcm750-clk.txt1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
28 - #clock-cells: should be 1.
30 Example: Clock controller node:
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Dnvidia,tegra124-dfll.txt3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
7 the fast CPU cluster. It consists of a free-running voltage controlled
10 communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
13 - compatible : should be one of:
14 - "nvidia,tegra124-dfll": for Tegra124
15 - "nvidia,tegra210-dfll": for Tegra210
16 - reg : Defines the following set of registers, in the order listed:
17 - registers for the DFLL control logic.
18 - registers for the I2C output logic.
[all …]
Drenesas,cpg-clocks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG)
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
16 The CPG may also provide a Clock Domain for SoC devices, in combination with
22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
23 - const: renesas,r8a7740-cpg-clocks # R-Mobile A1
[all …]
Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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Dkeystone-pll.txt1 Status: Unstable - ABI compatibility may be broken in the future
9 This binding uses the common clock binding[1].
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - #clock-cells : from common clock binding; shall be set to 0.
15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
16 - clocks : parent clock phandle
17 - reg - pll control0 and pll multipler registers
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
[all …]
/linux-5.10/Documentation/devicetree/bindings/mfd/
Dallwinner,sun6i-a31-prcm.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mfd/allwinner,sun6i-a31-prcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
17 const: allwinner,sun6i-a31-prcm
29 - allwinner,sun4i-a10-mod0-clk
30 - allwinner,sun6i-a31-apb0-clk
31 - allwinner,sun6i-a31-apb0-gates-clk
[all …]
Dallwinner,sun8i-a23-prcm.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/mfd/allwinner,sun8i-a23-prcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
17 const: allwinner,sun8i-a23-prcm
29 - fixed-factor-clock
30 - allwinner,sun8i-a23-apb0-clk
31 - allwinner,sun8i-a23-apb0-gates-clk
[all …]
/linux-5.10/arch/arm64/boot/dts/amd/
Damd-seattle-clks.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <100000000>;
12 clock-output-names = "adl3clk_100mhz";
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <375000000>;
19 clock-output-names = "ccpclk_375mhz";
23 compatible = "fixed-clock";
[all …]
/linux-5.10/Documentation/devicetree/bindings/mmc/
Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
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/linux-5.10/Documentation/devicetree/bindings/phy/
Dti,phy-am654-serdes.txt4 - compatible: Should be "ti,phy-am654-serdes"
5 - reg : Address and length of the register set for the device.
6 - #phy-cells: determine the number of cells that should be given in the
9 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes
12 0 - USB3
13 1 - PCIe0 Lane0
14 2 - ICSS2 SGMII Lane0
16 0 - PCIe1 Lane0
17 1 - PCIe0 Lane1
18 2 - ICSS2 SGMII Lane1
[all …]
Dphy-rockchip-inno-usb2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-usb2phy
16 - rockchip,rk3228-usb2phy
17 - rockchip,rk3328-usb2phy
18 - rockchip,rk3366-usb2phy
19 - rockchip,rk3399-usb2phy
[all …]
/linux-5.10/arch/arm64/boot/dts/arm/
Djuno-clocks.dtsi4 * Copyright (c) 2013-2014 ARM Ltd
12 compatible = "fixed-clock";
13 #clock-cells = <0>;
14 clock-frequency = <7372800>;
15 clock-output-names = "juno:uartclk";
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <48000000>;
22 clock-output-names = "clk48mhz";
26 compatible = "fixed-clock";
[all …]
/linux-5.10/arch/arm64/boot/dts/zte/
Dzx296718.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/input/input.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/clock/zx296718-clock.h>
51 #address-cells = <1>;
52 #size-cells = <1>;
53 interrupt-parent = <&gic>;
67 #address-cells = <2>;
68 #size-cells = <0>;
[all …]
/linux-5.10/Documentation/devicetree/bindings/rtc/
Dallwinner,sun6i-a31-rtc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/allwinner,sun6i-a31-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#clock-cells":
19 - const: allwinner,sun6i-a31-rtc
20 - const: allwinner,sun8i-a23-rtc
21 - const: allwinner,sun8i-h3-rtc
[all …]

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