Lines Matching +full:clock +full:- +full:output +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/stih410-clks.h>
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
14 clock-output-names = "CLK_SYSIN";
17 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <0>;
24 #address-cells = <1>;
25 #size-cells = <1>;
28 compatible = "st,stih410-clk", "simple-bus";
33 clockgen-a9@92b0000 {
34 compatible = "st,clkgen-c32";
37 clockgen_a9_pll: clockgen-a9-pll {
38 #clock-cells = <1>;
39 compatible = "st,stih407-clkgen-plla9";
43 clock-output-names = "clockgen-a9-pll-odf";
50 clk_m_a9: clk-m-a9@92b0000 {
51 #clock-cells = <0>;
52 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
60 * ARM Peripheral clock for timers
62 arm_periph_clk: clk-m-a9-periphs {
63 #clock-cells = <0>;
64 compatible = "fixed-factor-clock";
66 clock-div = <2>;
67 clock-mult = <1>;
71 clockgen-a@90ff000 {
72 compatible = "st,clkgen-c32";
75 clk_s_a0_pll: clk-s-a0-pll {
76 #clock-cells = <1>;
77 compatible = "st,clkgen-pll0";
81 clock-output-names = "clk-s-a0-pll-ofd-0";
82 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
85 clk_s_a0_flexgen: clk-s-a0-flexgen {
88 #clock-cells = <1>;
93 clock-output-names = "clk-ic-lmi0",
94 "clk-ic-lmi1";
95 clock-critical = <CLK_IC_LMI0>;
99 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
100 #clock-cells = <1>;
101 compatible = "st,quadfs-pll";
106 clock-output-names = "clk-s-c0-fs0-ch0",
107 "clk-s-c0-fs0-ch1",
108 "clk-s-c0-fs0-ch2",
109 "clk-s-c0-fs0-ch3";
110 clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
113 clk_s_c0: clockgen-c@9103000 {
114 compatible = "st,clkgen-c32";
117 clk_s_c0_pll0: clk-s-c0-pll0 {
118 #clock-cells = <1>;
119 compatible = "st,clkgen-pll0";
123 clock-output-names = "clk-s-c0-pll0-odf-0";
124 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
127 clk_s_c0_pll1: clk-s-c0-pll1 {
128 #clock-cells = <1>;
129 compatible = "st,clkgen-pll1";
133 clock-output-names = "clk-s-c0-pll1-odf-0";
136 clk_s_c0_flexgen: clk-s-c0-flexgen {
137 #clock-cells = <1>;
148 clock-output-names = "clk-icn-gpu",
149 "clk-fdma",
150 "clk-nand",
151 "clk-hva",
152 "clk-proc-stfe",
153 "clk-proc-tp",
154 "clk-rx-icn-dmu",
155 "clk-rx-icn-hva",
156 "clk-icn-cpu",
157 "clk-tx-icn-dmu",
158 "clk-mmc-0",
159 "clk-mmc-1",
160 "clk-jpegdec",
161 "clk-ext2fa9",
162 "clk-ic-bdisp-0",
163 "clk-ic-bdisp-1",
164 "clk-pp-dmu",
165 "clk-vid-dmu",
166 "clk-dss-lpc",
167 "clk-st231-aud-0",
168 "clk-st231-gp-1",
169 "clk-st231-dmu",
170 "clk-icn-lmi",
171 "clk-tx-icn-disp-1",
172 "clk-icn-sbc",
173 "clk-stfe-frc2",
174 "clk-eth-phy",
175 "clk-eth-ref-phyclk",
176 "clk-flash-promip",
177 "clk-main-disp",
178 "clk-aux-disp",
179 "clk-compo-dvp",
180 "clk-tx-icn-hades",
181 "clk-rx-icn-hades",
182 "clk-icn-reg-16",
183 "clk-pp-hades",
184 "clk-clust-hades",
185 "clk-hwpe-hades",
186 "clk-fc-hades";
187 clock-critical = <CLK_PROC_STFE>,
195 * ARM Peripheral clock for timers
197 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
198 #clock-cells = <0>;
199 compatible = "fixed-factor-clock";
203 clock-output-names = "clk-m-a9-ext2f-div2";
205 clock-div = <2>;
206 clock-mult = <1>;
211 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
212 #clock-cells = <1>;
218 clock-output-names = "clk-s-d0-fs0-ch0",
219 "clk-s-d0-fs0-ch1",
220 "clk-s-d0-fs0-ch2",
221 "clk-s-d0-fs0-ch3";
224 clockgen-d0@9104000 {
225 compatible = "st,clkgen-c32";
228 clk_s_d0_flexgen: clk-s-d0-flexgen {
229 #clock-cells = <1>;
230 compatible = "st,flexgen-audio", "st,flexgen";
238 clock-output-names = "clk-pcm-0",
239 "clk-pcm-1",
240 "clk-pcm-2",
241 "clk-spdiff",
242 "clk-pcmr10-master",
243 "clk-usb2-phy";
247 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
248 #clock-cells = <1>;
254 clock-output-names = "clk-s-d2-fs0-ch0",
255 "clk-s-d2-fs0-ch1",
256 "clk-s-d2-fs0-ch2",
257 "clk-s-d2-fs0-ch3";
260 clockgen-d2@9106000 {
261 compatible = "st,clkgen-c32";
264 clk_s_d2_flexgen: clk-s-d2-flexgen {
265 #clock-cells = <1>;
266 compatible = "st,flexgen-video", "st,flexgen";
276 clock-output-names = "clk-pix-main-disp",
277 "clk-pix-pip",
278 "clk-pix-gdp1",
279 "clk-pix-gdp2",
280 "clk-pix-gdp3",
281 "clk-pix-gdp4",
282 "clk-pix-aux-disp",
283 "clk-denc",
284 "clk-pix-hddac",
285 "clk-hddac",
286 "clk-sddac",
287 "clk-pix-dvo",
288 "clk-dvo",
289 "clk-pix-hdmi",
290 "clk-tmds-hdmi",
291 "clk-ref-hdmiphy";
295 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
296 #clock-cells = <1>;
302 clock-output-names = "clk-s-d3-fs0-ch0",
303 "clk-s-d3-fs0-ch1",
304 "clk-s-d3-fs0-ch2",
305 "clk-s-d3-fs0-ch3";
308 clockgen-d3@9107000 {
309 compatible = "st,clkgen-c32";
312 clk_s_d3_flexgen: clk-s-d3-flexgen {
313 #clock-cells = <1>;
322 clock-output-names = "clk-stfe-frc1",
323 "clk-tsout-0",
324 "clk-tsout-1",
325 "clk-mchi",
326 "clk-vsens-compo",
327 "clk-frc1-remote",
328 "clk-lpc-0",
329 "clk-lpc-1";