Lines Matching +full:clock +full:- +full:output +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/stih418-clks.h>
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
14 clock-output-names = "CLK_SYSIN";
17 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <0>;
24 #address-cells = <1>;
25 #size-cells = <1>;
28 compatible = "st,stih418-clk", "simple-bus";
33 clockgen-a9@92b0000 {
34 compatible = "st,clkgen-c32";
37 clockgen_a9_pll: clockgen-a9-pll {
38 #clock-cells = <1>;
39 compatible = "st,stih418-clkgen-plla9";
43 clock-output-names = "clockgen-a9-pll-odf";
50 clk_m_a9: clk-m-a9@92b0000 {
51 #clock-cells = <0>;
52 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
61 * ARM Peripheral clock for timers
63 arm_periph_clk: clk-m-a9-periphs {
64 #clock-cells = <0>;
65 compatible = "fixed-factor-clock";
67 clock-div = <2>;
68 clock-mult = <1>;
72 clockgen-a@90ff000 {
73 compatible = "st,clkgen-c32";
76 clk_s_a0_pll: clk-s-a0-pll {
77 #clock-cells = <1>;
78 compatible = "st,clkgen-pll0";
82 clock-output-names = "clk-s-a0-pll-ofd-0";
85 clk_s_a0_flexgen: clk-s-a0-flexgen {
88 #clock-cells = <1>;
93 clock-output-names = "clk-ic-lmi0",
94 "clk-ic-lmi1";
98 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
99 #clock-cells = <1>;
100 compatible = "st,quadfs-pll";
105 clock-output-names = "clk-s-c0-fs0-ch0",
106 "clk-s-c0-fs0-ch1",
107 "clk-s-c0-fs0-ch2",
108 "clk-s-c0-fs0-ch3";
111 clk_s_c0: clockgen-c@9103000 {
112 compatible = "st,clkgen-c32";
115 clk_s_c0_pll0: clk-s-c0-pll0 {
116 #clock-cells = <1>;
117 compatible = "st,clkgen-pll0";
121 clock-output-names = "clk-s-c0-pll0-odf-0";
124 clk_s_c0_pll1: clk-s-c0-pll1 {
125 #clock-cells = <1>;
126 compatible = "st,clkgen-pll1";
130 clock-output-names = "clk-s-c0-pll1-odf-0";
133 clk_s_c0_flexgen: clk-s-c0-flexgen {
134 #clock-cells = <1>;
145 clock-output-names = "clk-icn-gpu",
146 "clk-fdma",
147 "clk-nand",
148 "clk-hva",
149 "clk-proc-stfe",
150 "clk-tp",
151 "clk-rx-icn-dmu",
152 "clk-rx-icn-hva",
153 "clk-icn-cpu",
154 "clk-tx-icn-dmu",
155 "clk-mmc-0",
156 "clk-mmc-1",
157 "clk-jpegdec",
158 "clk-icn-reg",
159 "clk-proc-bdisp-0",
160 "clk-proc-bdisp-1",
161 "clk-pp-dmu",
162 "clk-vid-dmu",
163 "clk-dss-lpc",
164 "clk-st231-aud-0",
165 "clk-st231-gp-1",
166 "clk-st231-dmu",
167 "clk-icn-lmi",
168 "clk-tx-icn-1",
169 "clk-icn-sbc",
170 "clk-stfe-frc2",
171 "clk-eth-phyref",
172 "clk-eth-ref-phyclk",
173 "clk-flash-promip",
174 "clk-main-disp",
175 "clk-aux-disp",
176 "clk-compo-dvp",
177 "clk-tx-icn-hades",
178 "clk-rx-icn-hades",
179 "clk-icn-reg-16",
180 "clk-pp-hevc",
181 "clk-clust-hevc",
182 "clk-hwpe-hevc",
183 "clk-fc-hevc",
184 "clk-proc-mixer",
185 "clk-proc-sc",
186 "clk-avsp-hevc";
189 * ARM Peripheral clock for timers
191 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
192 #clock-cells = <0>;
193 compatible = "fixed-factor-clock";
197 clock-output-names = "clk-m-a9-ext2f-div2";
199 clock-div = <2>;
200 clock-mult = <1>;
205 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
206 #clock-cells = <1>;
212 clock-output-names = "clk-s-d0-fs0-ch0",
213 "clk-s-d0-fs0-ch1",
214 "clk-s-d0-fs0-ch2",
215 "clk-s-d0-fs0-ch3";
218 clockgen-d0@9104000 {
219 compatible = "st,clkgen-c32";
222 clk_s_d0_flexgen: clk-s-d0-flexgen {
223 #clock-cells = <1>;
224 compatible = "st,flexgen-audio", "st,flexgen";
232 clock-output-names = "clk-pcm-0",
233 "clk-pcm-1",
234 "clk-pcm-2",
235 "clk-spdiff",
236 "clk-pcmr10-master",
237 "clk-usb2-phy";
241 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
242 #clock-cells = <1>;
248 clock-output-names = "clk-s-d2-fs0-ch0",
249 "clk-s-d2-fs0-ch1",
250 "clk-s-d2-fs0-ch2",
251 "clk-s-d2-fs0-ch3";
254 clockgen-d2@9106000 {
255 compatible = "st,clkgen-c32";
258 clk_s_d2_flexgen: clk-s-d2-flexgen {
259 #clock-cells = <1>;
260 compatible = "st,flexgen-video", "st,flexgen";
270 clock-output-names = "clk-pix-main-disp",
275 "clk-tmds-hdmi-div2",
276 "clk-pix-aux-disp",
277 "clk-denc",
278 "clk-pix-hddac",
279 "clk-hddac",
280 "clk-sddac",
281 "clk-pix-dvo",
282 "clk-dvo",
283 "clk-pix-hdmi",
284 "clk-tmds-hdmi",
285 "clk-ref-hdmiphy",
292 "", "clk-vp9";
296 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
297 #clock-cells = <1>;
303 clock-output-names = "clk-s-d3-fs0-ch0",
304 "clk-s-d3-fs0-ch1",
305 "clk-s-d3-fs0-ch2",
306 "clk-s-d3-fs0-ch3";
309 clockgen-d3@9107000 {
310 compatible = "st,clkgen-c32";
313 clk_s_d3_flexgen: clk-s-d3-flexgen {
314 #clock-cells = <1>;
323 clock-output-names = "clk-stfe-frc1",
324 "clk-tsout-0",
325 "clk-tsout-1",
326 "clk-mchi",
327 "clk-vsens-compo",
328 "clk-frc1-remote",
329 "clk-lpc-0",
330 "clk-lpc-1";