Lines Matching +full:clock +full:- +full:output +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/stih407-clks.h>
10 clk_sysin: clk-sysin {
11 #clock-cells = <0>;
12 compatible = "fixed-clock";
13 clock-frequency = <30000000>;
16 clk_tmdsout_hdmi: clk-tmdsout-hdmi {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <0>;
23 #address-cells = <1>;
24 #size-cells = <1>;
30 clockgen-a9@92b0000 {
31 compatible = "st,clkgen-c32";
34 clockgen_a9_pll: clockgen-a9-pll {
35 #clock-cells = <1>;
36 compatible = "st,stih407-clkgen-plla9";
40 clock-output-names = "clockgen-a9-pll-odf";
47 clk_m_a9: clk-m-a9@92b0000 {
48 #clock-cells = <0>;
49 compatible = "st,stih407-clkgen-a9-mux";
59 * ARM Peripheral clock for timers
61 arm_periph_clk: clk-m-a9-periphs {
62 #clock-cells = <0>;
63 compatible = "fixed-factor-clock";
66 clock-div = <2>;
67 clock-mult = <1>;
71 clockgen-a@90ff000 {
72 compatible = "st,clkgen-c32";
75 clk_s_a0_pll: clk-s-a0-pll {
76 #clock-cells = <1>;
77 compatible = "st,clkgen-pll0";
81 clock-output-names = "clk-s-a0-pll-ofd-0";
82 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
85 clk_s_a0_flexgen: clk-s-a0-flexgen {
88 #clock-cells = <1>;
93 clock-output-names = "clk-ic-lmi0";
94 clock-critical = <CLK_IC_LMI0>;
98 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
99 #clock-cells = <1>;
100 compatible = "st,quadfs-pll";
105 clock-output-names = "clk-s-c0-fs0-ch0",
106 "clk-s-c0-fs0-ch1",
107 "clk-s-c0-fs0-ch2",
108 "clk-s-c0-fs0-ch3";
109 clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
112 clk_s_c0: clockgen-c@9103000 {
113 compatible = "st,clkgen-c32";
116 clk_s_c0_pll0: clk-s-c0-pll0 {
117 #clock-cells = <1>;
118 compatible = "st,clkgen-pll0";
122 clock-output-names = "clk-s-c0-pll0-odf-0";
123 clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
126 clk_s_c0_pll1: clk-s-c0-pll1 {
127 #clock-cells = <1>;
128 compatible = "st,clkgen-pll1";
132 clock-output-names = "clk-s-c0-pll1-odf-0";
135 clk_s_c0_flexgen: clk-s-c0-flexgen {
136 #clock-cells = <1>;
147 clock-output-names = "clk-icn-gpu",
148 "clk-fdma",
149 "clk-nand",
150 "clk-hva",
151 "clk-proc-stfe",
152 "clk-proc-tp",
153 "clk-rx-icn-dmu",
154 "clk-rx-icn-hva",
155 "clk-icn-cpu",
156 "clk-tx-icn-dmu",
157 "clk-mmc-0",
158 "clk-mmc-1",
159 "clk-jpegdec",
160 "clk-ext2fa9",
161 "clk-ic-bdisp-0",
162 "clk-ic-bdisp-1",
163 "clk-pp-dmu",
164 "clk-vid-dmu",
165 "clk-dss-lpc",
166 "clk-st231-aud-0",
167 "clk-st231-gp-1",
168 "clk-st231-dmu",
169 "clk-icn-lmi",
170 "clk-tx-icn-disp-1",
171 "clk-icn-sbc",
172 "clk-stfe-frc2",
173 "clk-eth-phy",
174 "clk-eth-ref-phyclk",
175 "clk-flash-promip",
176 "clk-main-disp",
177 "clk-aux-disp",
178 "clk-compo-dvp";
179 clock-critical = <CLK_PROC_STFE>,
187 * ARM Peripheral clock for timers
189 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
190 #clock-cells = <0>;
191 compatible = "fixed-factor-clock";
195 clock-output-names = "clk-m-a9-ext2f-div2";
197 clock-div = <2>;
198 clock-mult = <1>;
203 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
204 #clock-cells = <1>;
210 clock-output-names = "clk-s-d0-fs0-ch0",
211 "clk-s-d0-fs0-ch1",
212 "clk-s-d0-fs0-ch2",
213 "clk-s-d0-fs0-ch3";
216 clockgen-d0@9104000 {
217 compatible = "st,clkgen-c32";
220 clk_s_d0_flexgen: clk-s-d0-flexgen {
221 #clock-cells = <1>;
222 compatible = "st,flexgen-audio", "st,flexgen";
230 clock-output-names = "clk-pcm-0",
231 "clk-pcm-1",
232 "clk-pcm-2",
233 "clk-spdiff";
237 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
238 #clock-cells = <1>;
244 clock-output-names = "clk-s-d2-fs0-ch0",
245 "clk-s-d2-fs0-ch1",
246 "clk-s-d2-fs0-ch2",
247 "clk-s-d2-fs0-ch3";
250 clockgen-d2@9106000 {
251 compatible = "st,clkgen-c32";
254 clk_s_d2_flexgen: clk-s-d2-flexgen {
255 #clock-cells = <1>;
256 compatible = "st,flexgen-video", "st,flexgen";
266 clock-output-names = "clk-pix-main-disp",
267 "clk-pix-pip",
268 "clk-pix-gdp1",
269 "clk-pix-gdp2",
270 "clk-pix-gdp3",
271 "clk-pix-gdp4",
272 "clk-pix-aux-disp",
273 "clk-denc",
274 "clk-pix-hddac",
275 "clk-hddac",
276 "clk-sddac",
277 "clk-pix-dvo",
278 "clk-dvo",
279 "clk-pix-hdmi",
280 "clk-tmds-hdmi",
281 "clk-ref-hdmiphy";
285 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
286 #clock-cells = <1>;
292 clock-output-names = "clk-s-d3-fs0-ch0",
293 "clk-s-d3-fs0-ch1",
294 "clk-s-d3-fs0-ch2",
295 "clk-s-d3-fs0-ch3";
298 clockgen-d3@9107000 {
299 compatible = "st,clkgen-c32";
302 clk_s_d3_flexgen: clk-s-d3-flexgen {
303 #clock-cells = <1>;
312 clock-output-names = "clk-stfe-frc1",
313 "clk-tsout-0",
314 "clk-tsout-1",
315 "clk-mchi",
316 "clk-vsens-compo",
317 "clk-frc1-remote",
318 "clk-lpc-0",
319 "clk-lpc-1";