| /linux-3.3/arch/arm/boot/dts/ |
| D | picoxcell-pc3x3.dtsi | 17 #address-cells = <1>;
18 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,1176jz-s";
26 cpu-clock = <&arm_clk>, "cpu";
28 d-cache-line-size = <32>;
29 d-cache-size = <32768>;
30 i-cache-line-size = <32>;
31 i-cache-size = <32768>;
[all …]
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| D | tegra-cardhu.dts | 1 /dts-v1/;
14 clock-frequency = < 408000000 >;
18 clock-frequency = <100000>;
22 clock-frequency = <100000>;
26 clock-frequency = <100000>;
30 clock-frequency = <100000>;
34 clock-frequency = <100000>;
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| D | tegra-paz00.dts | 1 /dts-v1/;
14 clock-frequency = <400000>;
18 clock-frequency = <400000>;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 clock-frequency = <80000>;
32 request-gpios = <&gpio 170 0>;
33 slave-addr = <138>;
37 clock-frequency = <400000>;
41 clock-frequency = <216000000>;
[all …]
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| D | tegra-ventana.dts | 1 /dts-v1/;
14 clock-frequency = <400000>;
18 clock-frequency = <400000>;
22 clock-frequency = <400000>;
26 clock-frequency = <400000>;
42 clock-frequency = < 216000000 >;
58 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
59 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
60 power-gpios = <&gpio 70 0>; /* gpio PI6 */
64 support-8bit;
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| D | tegra-seaboard.dts | 1 /dts-v1/;
15 clock-frequency = <400000>;
19 clock-frequency = <400000>;
23 clock-frequency = <400000>;
27 clock-frequency = <400000>;
48 clock-frequency = < 216000000 >;
64 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
65 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
66 power-gpios = <&gpio 70 0>; /* gpio PI6 */
70 support-8bit;
[all …]
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| D | tegra-harmony.dts | 1 /dts-v1/;
14 clock-frequency = <400000>;
21 gpio-controller;
22 #gpio-cells = <2>;
25 gpio-cfg = < 0x8000 0x8000 0 0x8000 0x8000 >;
30 clock-frequency = <400000>;
34 clock-frequency = <400000>;
38 clock-frequency = <400000>;
42 compatible = "nvidia,harmony-sound", "nvidia,tegra-wm8903";
44 spkr-en-gpios = <&codec 2 0>;
[all …]
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| D | tegra-trimslice.dts | 1 /dts-v1/;
14 clock-frequency = <400000>;
18 clock-frequency = <400000>;
22 clock-frequency = <400000>;
30 clock-frequency = < 216000000 >;
62 cd-gpios = <&gpio 121 0>;
63 wp-gpios = <&gpio 122 0>;
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| /linux-3.3/arch/arm/mach-bcmring/csp/chipc/ |
| D | chipcHw.c | 2 * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
19 * @brief Low level Various CHIP clock controlling routines
23 * These routines provide basic clock controlling functionality only.
27 /* ---- Include Files ---------------------------------------------------- */
39 /* ---- Private Constants and Types --------------------------------------- */
45 /* Local definition of clock type */
46 #define PLL_CLOCK 1 /* PLL Clock */
47 #define NON_PLL_CLOCK 2 /* Divider clock */
54 * @brief Set clock fequency for miscellaneous configurable clocks
56 * This function sets clock frequency
[all …]
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| /linux-3.3/include/linux/ |
| D | timex.h | 28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
35 * Revised status codes and structures for external clock and PPS
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
61 * syscall interface - used (mainly by NTP daemon)
62 * to discipline kernel clock oscillator
67 long freq; /* frequency offset (scaled ppm) */
[all …]
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| /linux-3.3/Documentation/devicetree/bindings/net/can/ |
| D | sja1000.txt | 5 - compatible : should be "nxp,sja1000".
7 - reg : should specify the chip select, address offset and size required
10 - interrupts: property with a value describing the interrupt source
15 - nxp,external-clock-frequency : Frequency of the external oscillator
16 clock in Hz. Note that the internal clock frequency used by the
20 - nxp,tx-output-mode : operation mode of the TX output control logic:
21 <0x0> : bi-phase output mode
24 <0x3> : clock output mode
26 - nxp,tx-output-config : TX output pin configuration:
28 <0x02> : TX0 pull-down (default)
[all …]
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| D | cc770.txt | 8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
14 - interrupts : property with a value describing the interrupt source
19 - bosch,external-clock-frequency : frequency of the external oscillator
20 clock in Hz. Note that the internal clock frequency used by the
24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
31 - bosch,disconnect-rx0-input : see data sheet.
33 - bosch,disconnect-rx1-input : see data sheet.
35 - bosch,disconnect-tx1-output : see data sheet.
[all …]
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| /linux-3.3/arch/powerpc/boot/dts/ |
| D | iss4xx-mpic.dts | 15 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
22 model = "ibm,iss-4xx";
23 compatible = "ibm,iss-4xx";
24 dcr-parent = <&{/cpus/cpu@0}>;
31 #address-cells = <1>;
32 #size-cells = <0>;
38 clock-frequency = <100000000>; // 100Mhz :-)
39 timebase-frequency = <100000000>;
[all …]
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| D | mpc836x_rdk.dts | 5 * Copyright 2007-2008 MontaVista Software, Inc.
15 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
35 #address-cells = <1>;
36 #size-cells = <0>;
41 d-cache-line-size = <32>;
42 i-cache-line-size = <32>;
43 d-cache-size = <32768>;
44 i-cache-size = <32768>;
[all …]
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| /linux-3.3/arch/arm/plat-samsung/include/plat/ |
| D | cpu-freq.h | 1 /* arch/arm/plat-samsung/include/plat/cpu-freq.h
3 * Copyright (c) 2006-2007 Simtec Electronics
7 * S3C CPU frequency scaling support - driver and board
21 * struct s3c_freq - frequency information (mainly for core drivers)
22 * @fclk: The FCLK frequency in Hz.
23 * @armclk: The ARMCLK frequency in Hz.
24 * @hclk_tns: HCLK cycle time in 10ths of nano-seconds.
25 * @hclk: The HCLK frequency in Hz.
26 * @pclk: The PCLK frequency in Hz.
28 * This contains the frequency information about the current configuration
[all …]
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| /linux-3.3/Documentation/devicetree/bindings/c6x/ |
| D | clocks.txt | 1 C6X PLL Clock Controllers
2 -------------------------
4 This is a first-cut support for the SoC clock controllers. This is still
6 clock support is added to the kernel.
10 - compatible: "ti,c64x+pll"
11 May also have SoC-specific value to support SoC-specific initialization
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
[all …]
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| /linux-3.3/drivers/cpufreq/ |
| D | elanfreq.c | 15 * 2002-02-13: - initial revision for 2.4.18-pre9 by Robert Schwebel
37 int clock; /* frequency in kHz */ member
39 int val80h; /* CPU Clock Speed Register */
73 * Finds out at which frequency the CPU of the Elan SOC runs
81 u8 clockspeed_reg; /* Clock Speed Register */ in elanfreq_get_cpu_frequency()
91 /* Are we in CPU clock multiplied mode (66/99 MHz)? */ in elanfreq_get_cpu_frequency()
108 * elanfreq_set_cpu_frequency: Change the CPU core frequency
110 * @freq: frequency in kHz
112 * This function takes a frequency value and changes the CPU frequency
113 * according to this. Note that the frequency has to be checked by
[all …]
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| D | Kconfig | 1 menu "CPU Frequency scaling"
4 bool "CPU Frequency scaling"
6 CPU Frequency scaling allows you to change the clock speed of
8 the lower the CPU clock speed, the less power the CPU consumes.
11 clock speed, you need to either enable a dynamic cpufreq governor
14 For details, take a look at <file:Documentation/cpu-freq>.
24 tristate "CPU frequency translation statistics"
28 This driver exports CPU frequency statistics information through sysfs
37 bool "CPU frequency translation statistics details"
40 This will show detail CPU frequency translation table in sysfs file
[all …]
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| /linux-3.3/drivers/devfreq/ |
| D | Kconfig | 2 bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
7 operating frequency based on the device driver's policy.
14 However, because the clock frequencies of a single device are
17 clock frequency of the device, which is also attached
18 to a device by 1-to-1. The device registering devfreq takes the
19 responsiblity to "interpret" the representative frequency and
20 to set its every clock accordingly with the "target" callback
35 Chooses frequency based on the recent load on the device. Works
37 Simple-Ondemand should be able to provide busy/total counter
44 Sets the frequency at the maximum available frequency.
[all …]
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| /linux-3.3/arch/sparc/include/asm/ |
| D | bbc.h | 2 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
11 /* Register sizes are indicated by "B" (Byte, 1-byte),
12 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
25 #define BBC_CSC 0x0d /* [B] Clock Synthesizers Control*/
28 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
29 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
32 #define BBC_ES_FSL 0x1c /* [W] E* Frequency Switch Latency*/
37 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
38 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
39 #define BBC_I2C_1_S1 0x30 /* [B] I2C ctrlr-1 reg S1 */
[all …]
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| /linux-3.3/arch/arm/mach-pxa/include/mach/ |
| D | pxa3xx-regs.h | 2 * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
33 #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
34 #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
36 #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
45 #define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */
46 #define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */
47 #define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */
48 #define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */
49 #define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */
50 #define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */
[all …]
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| /linux-3.3/arch/arm/mach-pxa/ |
| D | clock-pxa3xx.c | 2 * linux/arch/arm/mach-pxa/clock-pxa3xx.c
16 #include <mach/pxa3xx-regs.h>
18 #include "clock.h"
20 /* Crystal clock: 13MHz */
23 /* Ring Oscillator Clock: 60MHz */
29 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
33 * Get the clock frequency as reflected by CCSR and the turbo flag.
61 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n", in pxa3xx_get_clk_frequency_khz()
64 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n", in pxa3xx_get_clk_frequency_khz()
66 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n", in pxa3xx_get_clk_frequency_khz()
[all …]
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| /linux-3.3/sound/drivers/vx/ |
| D | vx_uer.c | 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 * vx_modify_board_clock - tell the board that its clock has been modified
45 * vx_modify_board_inputs - resync audio inputs
57 * vx_read_one_cbit - read one bit from UER config
65 spin_lock_irqsave(&chip->lock, flags); in vx_read_one_cbit()
66 if (chip->type >= VX_TYPE_VXPOCKET) { in vx_read_one_cbit()
75 spin_unlock_irqrestore(&chip->lock, flags); in vx_read_one_cbit()
80 * vx_write_one_cbit - write one bit to UER config
88 spin_lock_irqsave(&chip->lock, flags); in vx_write_one_cbit()
96 spin_unlock_irqrestore(&chip->lock, flags); in vx_write_one_cbit()
[all …]
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| /linux-3.3/Documentation/cpu-freq/ |
| D | user-guide.txt | 1 CPU frequency and voltage scaling code in the Linux(TM) kernel
13 Clock scaling allows you to change the clock speed of the CPUs on the
15 the clock speed, the less power the CPU consumes.
19 ---------
41 -------
46 ARM-SA1100
47 ARM-SA1110
52 -------
56 AMD Elan - SC400, SC410
57 AMD mobile K6-2+
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| /linux-3.3/kernel/time/ |
| D | ntp.c | 19 #include "tick-internal.h"
41 * phase-lock loop variables
45 * clock synchronization status
47 * (TIME_ERROR prevents overwriting the CMOS clock)
51 /* clock status bits: */
69 /* frequency offset (scaled nsecs/secs): */
77 /* constant (boot-param configurable) NTP tick adjustment (upscaled) */
83 * The following variables are used when a pulse-per-second (PPS) signal
84 * is available. They establish the engineering parameters of the clock
102 static s64 pps_freq; /* frequency offset (scaled ns/s) */
[all …]
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| /linux-3.3/Documentation/devicetree/bindings/spi/ |
| D | spi_oc_tiny.txt | 4 - compatible : should be "opencores,tiny-spi-rtlsvn2".
5 - gpios : should specify GPIOs used for chipselect.
7 - clock-frequency : input clock frequency to the core.
8 - baud-width: width, in bits, of the programmable divider used to scale
9 the input clock to SCLK.
11 The clock-frequency and baud-width properties are needed only if the divider
|