Lines Matching +full:clock +full:- +full:frequency
17 #address-cells = <1>;
18 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,1176jz-s";
26 cpu-clock = <&arm_clk>, "cpu";
28 d-cache-line-size = <32>;
29 d-cache-size = <32768>;
30 i-cache-line-size = <32>;
31 i-cache-size = <32768>;
36 #address-cells = <1>;
37 #size-cells = <1>;
41 #address-cells = <1>;
42 #size-cells = <0>;
44 compatible = "picochip,pc3x3-clk-gate";
46 tzprot_clk: clock@0 {
47 compatible = "picochip,pc3x3-gated-clk";
48 clock-outputs = "bus";
49 picochip,clk-disable-bit = <0>;
50 clock-frequency = <200000000>;
51 ref-clock = <&ref_clk>, "ref";
54 spi_clk: clock@1 {
55 compatible = "picochip,pc3x3-gated-clk";
56 clock-outputs = "bus";
57 picochip,clk-disable-bit = <1>;
58 clock-frequency = <200000000>;
59 ref-clock = <&ref_clk>, "ref";
62 dmac0_clk: clock@2 {
63 compatible = "picochip,pc3x3-gated-clk";
64 clock-outputs = "bus";
65 picochip,clk-disable-bit = <2>;
66 clock-frequency = <200000000>;
67 ref-clock = <&ref_clk>, "ref";
70 dmac1_clk: clock@3 {
71 compatible = "picochip,pc3x3-gated-clk";
72 clock-outputs = "bus";
73 picochip,clk-disable-bit = <3>;
74 clock-frequency = <200000000>;
75 ref-clock = <&ref_clk>, "ref";
78 ebi_clk: clock@4 {
79 compatible = "picochip,pc3x3-gated-clk";
80 clock-outputs = "bus";
81 picochip,clk-disable-bit = <4>;
82 clock-frequency = <200000000>;
83 ref-clock = <&ref_clk>, "ref";
86 ipsec_clk: clock@5 {
87 compatible = "picochip,pc3x3-gated-clk";
88 clock-outputs = "bus";
89 picochip,clk-disable-bit = <5>;
90 clock-frequency = <200000000>;
91 ref-clock = <&ref_clk>, "ref";
94 l2_clk: clock@6 {
95 compatible = "picochip,pc3x3-gated-clk";
96 clock-outputs = "bus";
97 picochip,clk-disable-bit = <6>;
98 clock-frequency = <200000000>;
99 ref-clock = <&ref_clk>, "ref";
102 trng_clk: clock@7 {
103 compatible = "picochip,pc3x3-gated-clk";
104 clock-outputs = "bus";
105 picochip,clk-disable-bit = <7>;
106 clock-frequency = <200000000>;
107 ref-clock = <&ref_clk>, "ref";
110 fuse_clk: clock@8 {
111 compatible = "picochip,pc3x3-gated-clk";
112 clock-outputs = "bus";
113 picochip,clk-disable-bit = <8>;
114 clock-frequency = <200000000>;
115 ref-clock = <&ref_clk>, "ref";
118 otp_clk: clock@9 {
119 compatible = "picochip,pc3x3-gated-clk";
120 clock-outputs = "bus";
121 picochip,clk-disable-bit = <9>;
122 clock-frequency = <200000000>;
123 ref-clock = <&ref_clk>, "ref";
127 arm_clk: clock@11 {
128 compatible = "picochip,pc3x3-pll";
130 picochip,min-freq = <140000000>;
131 picochip,max-freq = <700000000>;
132 ref-clock = <&ref_clk>, "ref";
133 clock-outputs = "cpu";
136 pclk: clock@12 {
137 compatible = "fixed-clock";
138 clock-outputs = "bus", "pclk";
139 clock-frequency = <200000000>;
140 ref-clock = <&ref_clk>, "ref";
145 compatible = "simple-bus";
146 #address-cells = <1>;
147 #size-cells = <1>;
153 interrupt-parent = <&vic0>;
158 compatible = "snps,dw-dmac";
160 interrupt-parent = <&vic0>;
165 compatible = "snps,dw-dmac";
167 interrupt-parent = <&vic0>;
171 vic0: interrupt-controller@60000 {
172 compatible = "arm,pl192-vic";
173 interrupt-controller;
175 #interrupt-cells = <1>;
178 vic1: interrupt-controller@64000 {
179 compatible = "arm,pl192-vic";
180 interrupt-controller;
182 #interrupt-cells = <1>;
185 fuse: picoxcell-fuse@80000 {
186 compatible = "picoxcell,fuse-pc3x3";
190 ssi: picoxcell-spi@90000 {
193 interrupt-parent = <&vic0>;
198 compatible = "picochip,spacc-ipsec";
200 interrupt-parent = <&vic0>;
202 ref-clock = <&ipsec_clk>, "ref";
206 compatible = "picochip,spacc-srtp";
208 interrupt-parent = <&vic0>;
213 compatible = "picochip,spacc-l2";
215 interrupt-parent = <&vic0>;
217 ref-clock = <&l2_clk>, "ref";
221 compatible = "simple-bus";
222 #address-cells = <1>;
223 #size-cells = <1>;
227 compatible = "picochip,pc3x2-rtc";
228 clock-freq = <200000000>;
230 interrupt-parent = <&vic0>;
235 compatible = "picochip,pc3x2-timer";
236 interrupt-parent = <&vic0>;
238 clock-freq = <200000000>;
243 compatible = "picochip,pc3x2-timer";
244 interrupt-parent = <&vic0>;
246 clock-freq = <200000000>;
251 compatible = "snps,dw-apb-gpio";
253 #address-cells = <1>;
254 #size-cells = <0>;
255 reg-io-width = <4>;
257 banka: gpio-controller@0 {
258 compatible = "snps,dw-apb-gpio-bank";
259 gpio-controller;
260 #gpio-cells = <2>;
261 gpio-generic,nr-gpio = <8>;
263 regoffset-dat = <0x50>;
264 regoffset-set = <0x00>;
265 regoffset-dirout = <0x04>;
268 bankb: gpio-controller@1 {
269 compatible = "snps,dw-apb-gpio-bank";
270 gpio-controller;
271 #gpio-cells = <2>;
272 gpio-generic,nr-gpio = <16>;
274 regoffset-dat = <0x54>;
275 regoffset-set = <0x0c>;
276 regoffset-dirout = <0x10>;
279 bankd: gpio-controller@2 {
280 compatible = "snps,dw-apb-gpio-bank";
281 gpio-controller;
282 #gpio-cells = <2>;
283 gpio-generic,nr-gpio = <30>;
285 regoffset-dat = <0x5c>;
286 regoffset-set = <0x24>;
287 regoffset-dirout = <0x28>;
292 compatible = "snps,dw-apb-uart";
294 interrupt-parent = <&vic1>;
296 clock-frequency = <3686400>;
297 reg-shift = <2>;
298 reg-io-width = <4>;
302 compatible = "snps,dw-apb-uart";
304 interrupt-parent = <&vic1>;
306 clock-frequency = <3686400>;
307 reg-shift = <2>;
308 reg-io-width = <4>;
312 compatible = "snps,dw-apb-wdg";
314 interrupt-parent = <&vic0>;
316 bus-clock = <&pclk>, "bus";
320 compatible = "picochip,pc3x2-timer";
321 interrupt-parent = <&vic0>;
323 clock-freq = <200000000>;
328 compatible = "picochip,pc3x2-timer";
329 interrupt-parent = <&vic0>;
331 clock-freq = <200000000>;
337 rwid-axi {
338 #address-cells = <1>;
339 #size-cells = <1>;
340 compatible = "simple-bus";
344 compatible = "simple-bus";
345 #address-cells = <2>;
346 #size-cells = <1>;
354 compatible = "picochip,axi2pico-pc3x3";
356 interrupt-parent = <&vic0>;
361 compatible = "picochip,otp-pc3x3";