include/mach/pxa3xx-regs.h

2  * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
33 #define PWER		__REG(0x40F50010)	/* Power Manager Wake-up Enable Register */
34 #define PWSR		__REG(0x40F50014)	/* Power Manager Wake-up Status Register */
36 #define DCDCSR		__REG(0x40F50080)	/* DC-DC Controller Status Register */
45 #define AD3ER		__REG(0x40f40008)	/* Application Subsystem Wake-Up from D3 Enable */
46 #define AD3SR		__REG(0x40f4000c)	/* Application Subsystem Wake-Up from D3 Status */
47 #define AD2D0ER		__REG(0x40f40010)	/* Application Subsystem Wake-Up from D2 to D0 Enable */
48 #define AD2D0SR		__REG(0x40f40014)	/* Application Subsystem Wake-Up from D2 to D0 Status */
49 #define AD2D1ER		__REG(0x40f40018)	/* Application Subsystem Wake-Up from D2 to D1 Enable */
50 #define AD2D1SR		__REG(0x40f4001c)	/* Application Subsystem Wake-Up from D2 to D1 Status */
51 #define AD1D0ER		__REG(0x40f40020)	/* Application Subsystem Wake-Up from D1 to D0 Enable */
52 #define AD1D0SR		__REG(0x40f40024)	/* Application Subsystem Wake-Up from D1 to D0 Status */
75  * Application Subsystem Wake-Up bits.
107  * AD3R/AD2R/AD1R bits.  R2-R5 are only defined for PXA320.
127  * Application Subsystem Clock
129 #define ACCR		__REG(0x41340000)	/* Application Subsystem Clock Configuration Register */
130 #define ACSR		__REG(0x41340004)	/* Application Subsystem Clock Status Register */
132 #define CKENA		__REG(0x4134000C)	/* A Clock Enable Register */
133 #define CKENB		__REG(0x41340010)	/* B Clock Enable Register */
134 #define AC97_DIV	__REG(0x41340014)	/* AC97 clock divisor value register */
138 #define ACCR_D0CS		(1 << 26)	/* D0 Mode Clock Select */
139 #define ACCR_PCCE		(1 << 11)	/* Power Mode Change Clock Enable */
140 #define ACCR_DDR_D0CS		(1 << 7)	/* DDR SDRAM clock frequency in D0CS (PXA31x only) */
142 #define ACCR_SMCFS_MASK		(0x7 << 23)	/* Static Memory Controller Frequency Select */
143 #define ACCR_SFLFS_MASK		(0x3 << 18)	/* Frequency Select for Internal Memory Controller */
144 #define ACCR_XSPCLK_MASK	(0x3 << 16)	/* Core Frequency during Frequency Change */
145 #define ACCR_HSS_MASK		(0x3 << 14)	/* System Bus-Clock Frequency Select */
146 #define ACCR_DMCFS_MASK		(0x3 << 12)	/* Dynamic Memory Controller Clock Frequency Select */
147 #define ACCR_XN_MASK		(0x7 << 8)	/* Core PLL Turbo-Mode-to-Run-Mode Ratio */
148 #define ACCR_XL_MASK		(0x1f)		/* Core PLL Run-Mode-to-Oscillator Ratio */
159  * Clock Enable Bit
161 #define CKEN_LCD	1	/* < LCD Clock Enable */
162 #define CKEN_USBH	2	/* < USB host clock enable */
163 #define CKEN_CAMERA	3	/* < Camera interface clock enable */
164 #define CKEN_NAND	4	/* < NAND Flash Controller Clock Enable */
165 #define CKEN_USB2	6	/* < USB 2.0 client clock enable. */
166 #define CKEN_DMC	8	/* < Dynamic Memory Controller clock enable */
167 #define CKEN_SMC	9	/* < Static Memory Controller clock enable */
168 #define CKEN_ISC	10	/* < Internal SRAM Controller clock enable */
169 #define CKEN_BOOT	11	/* < Boot rom clock enable */
170 #define CKEN_MMC1	12	/* < MMC1 Clock enable */
171 #define CKEN_MMC2	13	/* < MMC2 clock enable */
172 #define CKEN_KEYPAD	14	/* < Keypand Controller Clock Enable */
173 #define CKEN_CIR	15	/* < Consumer IR Clock Enable */
174 #define CKEN_USIM0	17	/* < USIM[0] Clock Enable */
175 #define CKEN_USIM1	18	/* < USIM[1] Clock Enable */
176 #define CKEN_TPM	19	/* < TPM clock enable */
177 #define CKEN_UDC	20	/* < UDC clock enable */
178 #define CKEN_BTUART	21	/* < BTUART clock enable */
179 #define CKEN_FFUART	22	/* < FFUART clock enable */
180 #define CKEN_STUART	23	/* < STUART clock enable */
181 #define CKEN_AC97	24	/* < AC97 clock enable */
182 #define CKEN_TOUCH	25	/* < Touch screen Interface Clock Enable */
183 #define CKEN_SSP1	26	/* < SSP1 clock enable */
184 #define CKEN_SSP2	27	/* < SSP2 clock enable */
185 #define CKEN_SSP3	28	/* < SSP3 clock enable */
186 #define CKEN_SSP4	29	/* < SSP4 clock enable */
187 #define CKEN_MSL0	30	/* < MSL0 clock enable */
188 #define CKEN_PWM0	32	/* < PWM[0] clock enable */
189 #define CKEN_PWM1	33	/* < PWM[1] clock enable */
190 #define CKEN_I2C	36	/* < I2C clock enable */
191 #define CKEN_INTC	38	/* < Interrupt controller clock enable */
192 #define CKEN_GPIO	39	/* < GPIO clock enable */
193 #define CKEN_1WIRE	40	/* < 1-wire clock enable */
194 #define CKEN_HSIO2	41	/* < HSIO2 clock enable */
195 #define CKEN_MINI_IM	48	/* < Mini-IM */
198 #define CKEN_MMC3	5	/* < MMC3 Clock Enable */
199 #define CKEN_MVED	43	/* < MVED clock enable */
201 /* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
202 #define CKEN_PXA300_GCU		42	/* Graphics controller clock enable */
203 #define CKEN_PXA320_GCU		7	/* Graphics controller clock enable */