Lines Matching +full:clock +full:- +full:frequency
2 * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
19 * @brief Low level Various CHIP clock controlling routines
23 * These routines provide basic clock controlling functionality only.
27 /* ---- Include Files ---------------------------------------------------- */
39 /* ---- Private Constants and Types --------------------------------------- */
45 /* Local definition of clock type */
46 #define PLL_CLOCK 1 /* PLL Clock */
47 #define NON_PLL_CLOCK 2 /* Divider clock */
54 * @brief Set clock fequency for miscellaneous configurable clocks
56 * This function sets clock frequency
58 * @return Configured clock frequency in hertz
62 chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ in chipcHw_getClockFrequency() argument
67 uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ in chipcHw_getClockFrequency()
68 uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ in chipcHw_getClockFrequency()
73 …if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDI… in chipcHw_getClockFrequency()
78 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> in chipcHw_getClockFrequency()
81 /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ in chipcHw_getClockFrequency()
89 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> in chipcHw_getClockFrequency()
95 ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> in chipcHw_getClockFrequency()
98 switch (clock) { in chipcHw_getClockFrequency()
100 pPLLReg = &pChipcHw->DDRClock; in chipcHw_getClockFrequency()
104 pPLLReg = &pChipcHw->ARMClock; in chipcHw_getClockFrequency()
108 pPLLReg = &pChipcHw->ESWClock; in chipcHw_getClockFrequency()
112 pPLLReg = &pChipcHw->VPMClock; in chipcHw_getClockFrequency()
116 pPLLReg = &pChipcHw->ESW125Clock; in chipcHw_getClockFrequency()
120 pPLLReg = &pChipcHw->UARTClock; in chipcHw_getClockFrequency()
124 pPLLReg = &pChipcHw->SDIO0Clock; in chipcHw_getClockFrequency()
128 pPLLReg = &pChipcHw->SDIO1Clock; in chipcHw_getClockFrequency()
132 pPLLReg = &pChipcHw->SPIClock; in chipcHw_getClockFrequency()
136 pPLLReg = &pChipcHw->ETMClock; in chipcHw_getClockFrequency()
140 pPLLReg = &pChipcHw->USBClock; in chipcHw_getClockFrequency()
144 pPLLReg = &pChipcHw->LCDClock; in chipcHw_getClockFrequency()
148 pPLLReg = &pChipcHw->APMClock; in chipcHw_getClockFrequency()
152 pClockCtrl = &pChipcHw->ACLKClock; in chipcHw_getClockFrequency()
153 pDependentClock = &pChipcHw->ARMClock; in chipcHw_getClockFrequency()
158 pClockCtrl = &pChipcHw->OTPClock; in chipcHw_getClockFrequency()
161 pClockCtrl = &pChipcHw->I2CClock; in chipcHw_getClockFrequency()
164 pClockCtrl = &pChipcHw->I2S0Clock; in chipcHw_getClockFrequency()
167 pClockCtrl = &pChipcHw->RTBUSClock; in chipcHw_getClockFrequency()
168 pDependentClock = &pChipcHw->ACLKClock; in chipcHw_getClockFrequency()
172 pClockCtrl = &pChipcHw->APM100Clock; in chipcHw_getClockFrequency()
173 pDependentClock = &pChipcHw->APMClock; in chipcHw_getClockFrequency()
178 pClockCtrl = &pChipcHw->TSCClock; in chipcHw_getClockFrequency()
181 pClockCtrl = &pChipcHw->LEDClock; in chipcHw_getClockFrequency()
184 pClockCtrl = &pChipcHw->I2S1Clock; in chipcHw_getClockFrequency()
189 /* Obtain PLL clock frequency */ in chipcHw_getClockFrequency()
191 /* Return crystal clock frequency when bypassed */ in chipcHw_getClockFrequency()
193 } else if (clock == chipcHw_CLOCK_DDR) { in chipcHw_getClockFrequency()
194 /* DDR frequency is configured in PLLDivider register */ in chipcHw_getClockFrequency()
195 …return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivide… in chipcHw_getClockFrequency()
197 /* From chip revision number B0, LCD clock is internally divided by 2 */ in chipcHw_getClockFrequency()
198 …if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)… in chipcHw_getClockFrequency()
201 /* Obtain PLL clock frequency using VCO dividers */ in chipcHw_getClockFrequency()
205 /* Obtain divider clock frequency */ in chipcHw_getClockFrequency()
210 /* Return crystal clock frequency when bypassed */ in chipcHw_getClockFrequency()
213 /* Identify the dependent clock frequency */ in chipcHw_getClockFrequency()
217 /* Use crystal clock frequency when dependent PLL clock is bypassed */ in chipcHw_getClockFrequency()
220 /* Obtain PLL clock frequency using VCO dividers */ in chipcHw_getClockFrequency()
226 if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { in chipcHw_getClockFrequency()
230 /* Use crystal clock frequency when dependent divider clock is bypassed */ in chipcHw_getClockFrequency()
233 /* Obtain divider clock frequency using XTAL dividers */ in chipcHw_getClockFrequency()
241 /* Dependent on crystal clock */ in chipcHw_getClockFrequency()
253 * @brief Set clock fequency for miscellaneous configurable clocks
255 * This function sets clock frequency
257 * @return Configured clock frequency in Hz
261 chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */ in chipcHw_setClockFrequency() argument
262 uint32_t freq /* [ IN ] Clock frequency in Hz */ in chipcHw_setClockFrequency()
267 uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ in chipcHw_setClockFrequency()
268 uint32_t desVcoFreqPll1Hz = 0; /* Desired VCO frequency for PLL1 in Hz */ in chipcHw_setClockFrequency()
269 uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ in chipcHw_setClockFrequency()
275 …if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDI… in chipcHw_setClockFrequency()
280 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> in chipcHw_setClockFrequency()
283 /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ in chipcHw_setClockFrequency()
289 /* Desired VCO frequency */ in chipcHw_setClockFrequency()
292 (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> in chipcHw_setClockFrequency()
297 ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> in chipcHw_setClockFrequency()
301 ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> in chipcHw_setClockFrequency()
304 switch (clock) { in chipcHw_setClockFrequency()
309 /* Dvide DDR_phy by two to obtain DDR_ctrl clock */ in chipcHw_setClockFrequency()
310 …ipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) … in chipcHw_setClockFrequency()
314 pPLLReg = &pChipcHw->DDRClock; in chipcHw_setClockFrequency()
319 pPLLReg = &pChipcHw->ARMClock; in chipcHw_setClockFrequency()
324 pPLLReg = &pChipcHw->ESWClock; in chipcHw_setClockFrequency()
332 …w->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (… in chipcHw_setClockFrequency()
336 pPLLReg = &pChipcHw->VPMClock; in chipcHw_setClockFrequency()
341 pPLLReg = &pChipcHw->ESW125Clock; in chipcHw_setClockFrequency()
346 pPLLReg = &pChipcHw->UARTClock; in chipcHw_setClockFrequency()
351 pPLLReg = &pChipcHw->SDIO0Clock; in chipcHw_setClockFrequency()
356 pPLLReg = &pChipcHw->SDIO1Clock; in chipcHw_setClockFrequency()
361 pPLLReg = &pChipcHw->SPIClock; in chipcHw_setClockFrequency()
366 pPLLReg = &pChipcHw->ETMClock; in chipcHw_setClockFrequency()
371 pPLLReg = &pChipcHw->USBClock; in chipcHw_setClockFrequency()
376 pPLLReg = &pChipcHw->LCDClock; in chipcHw_setClockFrequency()
381 pPLLReg = &pChipcHw->APMClock; in chipcHw_setClockFrequency()
386 pClockCtrl = &pChipcHw->ACLKClock; in chipcHw_setClockFrequency()
387 pDependentClock = &pChipcHw->ARMClock; in chipcHw_setClockFrequency()
393 pClockCtrl = &pChipcHw->OTPClock; in chipcHw_setClockFrequency()
396 pClockCtrl = &pChipcHw->I2CClock; in chipcHw_setClockFrequency()
399 pClockCtrl = &pChipcHw->I2S0Clock; in chipcHw_setClockFrequency()
402 pClockCtrl = &pChipcHw->RTBUSClock; in chipcHw_setClockFrequency()
403 pDependentClock = &pChipcHw->ACLKClock; in chipcHw_setClockFrequency()
407 pClockCtrl = &pChipcHw->APM100Clock; in chipcHw_setClockFrequency()
408 pDependentClock = &pChipcHw->APMClock; in chipcHw_setClockFrequency()
414 pClockCtrl = &pChipcHw->TSCClock; in chipcHw_setClockFrequency()
417 pClockCtrl = &pChipcHw->LEDClock; in chipcHw_setClockFrequency()
420 pClockCtrl = &pChipcHw->I2S1Clock; in chipcHw_setClockFrequency()
428 /* For DDR settings use only the PLL divider clock */ in chipcHw_setClockFrequency()
429 if (pPLLReg == &pChipcHw->DDRClock) { in chipcHw_setClockFrequency()
430 /* Set M1DIV for PLL1, which controls the DDR clock */ in chipcHw_setClockFrequency()
431 …reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER… in chipcHw_setClockFrequency()
432 /* Calculate expected frequency */ in chipcHw_setClockFrequency()
433 …freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider… in chipcHw_setClockFrequency()
435 /* From chip revision number B0, LCD clock is internally divided by 2 */ in chipcHw_setClockFrequency()
436 …if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)… in chipcHw_setClockFrequency()
440 /* Set MDIV to change the frequency */ in chipcHw_setClockFrequency()
443 /* Calculate expected frequency */ in chipcHw_setClockFrequency()
446 /* Wait for for atleast 200ns as per the protocol to change frequency */ in chipcHw_setClockFrequency()
450 /* Return the configured frequency */ in chipcHw_setClockFrequency()
455 /* Divider clock should not be bypassed */ in chipcHw_setClockFrequency()
459 /* Identify the clock source */ in chipcHw_setClockFrequency()
469 if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { in chipcHw_setClockFrequency()
485 /* Set the divider to obtain the required frequency */ in chipcHw_setClockFrequency()
499 * @brief Set VPM clock in sync with BUS clock for Chip Rev #A0
501 * This function does the phase adjustment between VPM and BUS clock
504 * -1 : On failure
518 …phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_… in vpmPhaseAlignA0()
524 /* Read the contents of VPM Clock resgister */ in vpmPhaseAlignA0()
525 phaseValue = pChipcHw->VPMClock; in vpmPhaseAlignA0()
530 …reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)… in vpmPhaseAlignA0()
534 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; in vpmPhaseAlignA0()
535 /* Read the contents of VPM Clock resgister. */ in vpmPhaseAlignA0()
536 phaseValue = pChipcHw->VPMClock; in vpmPhaseAlignA0()
539 phaseControl = (0x3F & (phaseControl - 1)); in vpmPhaseAlignA0()
553 return -1; in vpmPhaseAlignA0()
560 …reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)… in vpmPhaseAlignA0()
564 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; in vpmPhaseAlignA0()
565 phaseValue = pChipcHw->VPMClock; in vpmPhaseAlignA0()
572 return -1; in vpmPhaseAlignA0()
583 phaseControl = (0x3F & (phaseControl - 1)); in vpmPhaseAlignA0()
584 …reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)… in vpmPhaseAlignA0()
588 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; in vpmPhaseAlignA0()
589 phaseValue = pChipcHw->VPMClock; in vpmPhaseAlignA0()
596 return -1; in vpmPhaseAlignA0()
607 phaseControl = (0x3F & (phaseControl - 1)); in vpmPhaseAlignA0()
608 …reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)… in vpmPhaseAlignA0()
612 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; in vpmPhaseAlignA0()
613 phaseValue = pChipcHw->VPMClock; in vpmPhaseAlignA0()
620 return -1; in vpmPhaseAlignA0()
634 …reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)… in vpmPhaseAlignA0()
638 pChipcHw->VPMClock ^= in vpmPhaseAlignA0()
640 /* Read the contents of VPM Clock resgister. */ in vpmPhaseAlignA0()
641 phaseValue = pChipcHw->VPMClock; in vpmPhaseAlignA0()
644 phaseControl = (0x3F & (phaseControl - 1)); in vpmPhaseAlignA0()
656 return -1; in vpmPhaseAlignA0()
664 phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F); in vpmPhaseAlignA0()
668 …pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseCont… in vpmPhaseAlignA0()
670 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; in vpmPhaseAlignA0()
680 * @brief Set VPM clock in sync with BUS clock
682 * This function does the phase adjustment between VPM and BUS clock
685 * -1 : On failure
700 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; in chipcHw_vpmPhaseAlign()
715 phaseControl--; in chipcHw_vpmPhaseAlign()
718 pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; in chipcHw_vpmPhaseAlign()
723 …reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)… in chipcHw_vpmPhaseAlign()
727 pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; in chipcHw_vpmPhaseAlign()
734 pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; in chipcHw_vpmPhaseAlign()
735 return -1; in chipcHw_vpmPhaseAlign()
765 if ((num - denom) >= 0) { in chipcHw_divide()
767 num = num - denom; in chipcHw_divide()