| /qemu/tests/qemu-iotests/ |
| H A D | 142.out | 6 === Simple test for all cache modes ===
8 Testing: -drive file=TEST_DIR/t.qcow2,cache=none
12 Testing: -drive file=TEST_DIR/t.qcow2,cache=directsync
16 Testing: -drive file=TEST_DIR/t.qcow2,cache=writeback
20 Testing: -drive file=TEST_DIR/t.qcow2,cache=writethrough
24 Testing: -drive file=TEST_DIR/t.qcow2,cache=unsafe
28 Testing: -drive file=TEST_DIR/t.qcow2,cache=invalid_value
29 QEMU_PROG: -drive file=TEST_DIR/t.qcow2,cache=invalid_value: invalid cache option
32 === Check inheritance of cache modes ===
35 --- Configure cache modes on the command line ---
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| H A D | 142 | 3 # Test for configuring cache modes of arbitrary nodes (requires O_DIRECT)
43 # We test all cache modes anyway, but O_DIRECT needs to be supported
73 echo === Simple test for all cache modes ===
76 run_qemu -drive file="$TEST_IMG",cache=none
77 run_qemu -drive file="$TEST_IMG",cache=directsync
78 run_qemu -drive file="$TEST_IMG",cache=writeback
79 run_qemu -drive file="$TEST_IMG",cache=writethrough
80 run_qemu -drive file="$TEST_IMG",cache=unsafe
81 run_qemu -drive file="$TEST_IMG",cache=invalid_value
84 echo === Check inheritance of cache modes ===
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| H A D | 157.out | 6 Testing: cache='writeback' wce=''
7 Cache mode: writeback
8 Testing: cache='writeback' wce=',write-cache=auto'
9 Cache mode: writeback
10 Testing: cache='writeback' wce=',write-cache=on'
11 Cache mode: writeback
12 Testing: cache='writeback' wce=',write-cache=off'
13 Cache mode: writethrough
14 Testing: cache='writethrough' wce=''
15 Cache mode: writethrough
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| H A D | 103 | 4 # Test case for qcow2 metadata cache size specification
56 $QEMU_IO -c "open -o cache-size=1.25M,l2-cache-size=1M,refcount-cache-size=0.25M $TEST_IMG" \
58 # l2-cache-size may not exceed cache-size
59 $QEMU_IO -c "open -o cache-size=1M,l2-cache-size=2M $TEST_IMG" 2>&1 \
61 # refcount-cache-size may not exceed cache-size
62 $QEMU_IO -c "open -o cache-size=1M,refcount-cache-size=2M $TEST_IMG" 2>&1 \
66 $QEMU_IO -c "open -o cache-size=0,l2-cache-size=0,refcount-cache-size=0 $TEST_IMG" \
69 # Invalid cache entry sizes
70 $QEMU_IO -c "open -o l2-cache-entry-size=256 $TEST_IMG" \
72 $QEMU_IO -c "open -o l2-cache-entry-size=4242 $TEST_IMG" \
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| H A D | 026.out | 17 qemu-io: Failed to flush the L2 table cache: Input/output error
18 qemu-io: Failed to flush the refcount block cache: Input/output error
24 qemu-io: Failed to flush the L2 table cache: Input/output error
25 qemu-io: Failed to flush the refcount block cache: Input/output error
41 qemu-io: Failed to flush the L2 table cache: No space left on device
42 qemu-io: Failed to flush the refcount block cache: No space left on device
48 qemu-io: Failed to flush the L2 table cache: No space left on device
49 qemu-io: Failed to flush the refcount block cache: No space left on device
129 qemu-io: Failed to flush the L2 table cache: Input/output error
130 qemu-io: Failed to flush the refcount block cache: Input/output error
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| H A D | 026.out.nocache | 17 qemu-io: Failed to flush the L2 table cache: Input/output error
18 qemu-io: Failed to flush the refcount block cache: Input/output error
24 qemu-io: Failed to flush the L2 table cache: Input/output error
25 qemu-io: Failed to flush the refcount block cache: Input/output error
41 qemu-io: Failed to flush the L2 table cache: No space left on device
42 qemu-io: Failed to flush the refcount block cache: No space left on device
48 qemu-io: Failed to flush the L2 table cache: No space left on device
49 qemu-io: Failed to flush the refcount block cache: No space left on device
131 qemu-io: Failed to flush the L2 table cache: Input/output error
132 qemu-io: Failed to flush the refcount block cache: Input/output error
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| H A D | 137 | 84 -c "reopen -o cache-size=1M" \
85 -c "reopen -o l2-cache-size=512k" \
86 -c "reopen -o l2-cache-entry-size=512" \
87 -c "reopen -o l2-cache-entry-size=4k" \
88 -c "reopen -o l2-cache-entry-size=64k" \
89 -c "reopen -o refcount-cache-size=128k" \
90 -c "reopen -o cache-clean-interval=5" \
91 -c "reopen -o cache-clean-interval=0" \
92 -c "reopen -o cache-clean-interval=10" \
109 -c "reopen -o cache-size=1M,l2-cache-size=64k,refcount-cache-size=64k" \
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| H A D | 103.out | 8 qemu-io: can't open device TEST_DIR/t.IMGFMT: cache-size, l2-cache-size and refcount-cache-size may…
9 qemu-io: can't open device TEST_DIR/t.IMGFMT: l2-cache-size may not exceed cache-size
10 qemu-io: can't open device TEST_DIR/t.IMGFMT: refcount-cache-size may not exceed cache-size
11 qemu-io: can't open device TEST_DIR/t.IMGFMT: cache-size, l2-cache-size and refcount-cache-size may…
12 qemu-io: can't open device TEST_DIR/t.IMGFMT: L2 cache entry size must be a power of two between 51…
13 qemu-io: can't open device TEST_DIR/t.IMGFMT: L2 cache entry size must be a power of two between 51…
14 qemu-io: can't open device TEST_DIR/t.IMGFMT: L2 cache entry size must be a power of two between 51…
33 === Testing minimal L2 cache and COW ===
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| H A D | 172.out | 29 write-cache = "auto"
58 write-cache = "auto"
66 Cache mode: writeback
94 write-cache = "auto"
108 write-cache = "auto"
116 Cache mode: writeback
148 write-cache = "auto"
162 write-cache = "auto"
170 Cache mode: writeback
175 Cache mode: writeback
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| H A D | 186.out | 62 Cache mode: writeback
70 Cache mode: writeback
78 Cache mode: writeback
86 Cache mode: writeback
94 Cache mode: writeback
102 Cache mode: writeback
111 Cache mode: writeback
120 Cache mode: writeback
129 Cache mode: writeback
138 Cache mode: writeback
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| H A D | 137.out | 19 qemu-io: cache-size, l2-cache-size and refcount-cache-size may not be set at the same time
20 qemu-io: l2-cache-size may not exceed cache-size
21 qemu-io: refcount-cache-size may not exceed cache-size
22 qemu-io: L2 cache entry size must be a power of two between 512 and the cluster size (65536)
23 qemu-io: L2 cache entry size must be a power of two between 512 and the cluster size (65536)
24 qemu-io: Refcount cache size too big
28 qemu-io: Cache clean interval too big
30 qemu-io: L2 cache size too big
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| H A D | 157 | 88 for cache in "writeback" "writethrough"; do
89 for wce in "" ",write-cache=auto" ",write-cache=on" ",write-cache=off"; do
90 echo "Testing: cache='$cache' wce='$wce'"
92 | run_qemu $SYSEMU_EXTRA_ARGS -drive "$SYSEMU_DRIVE_ARG,cache=$cache" \
94 | grep -e "Testing" -e "Cache mode"
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| /qemu/migration/ |
| H A D | page_cache.c | 2 * Page cache for QEMU
3 * The cache is base on a hash of the page address
23 /* the page in cache will not be replaced in two cycles */
45 PageCache *cache; in cache_init() local
48 error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "cache size", in cache_init()
55 error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "cache size", in cache_init()
61 cache = g_try_malloc(sizeof(*cache)); in cache_init()
62 if (!cache) { in cache_init()
63 error_setg(errp, "Failed to allocate cache"); in cache_init()
66 cache->page_size = page_size; in cache_init()
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| H A D | page_cache.h | 2 * Page cache for QEMU
3 * The cache is base on a hash of the page address
18 /* Page cache for storing guest pages */
22 * cache_init: Initialize the page cache
25 * Returns new allocated cache or NULL on error
27 * @cache_size: cache size in bytes
28 * @page_size: cache page size
33 * cache_fini: free all cache resources
34 * @cache pointer to the PageCache struct
36 void cache_fini(PageCache *cache);
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| /qemu/include/exec/ |
| H A D | memory_ldst_cached.h.inc | 27 static inline uint16_t ADDRESS_SPACE_LD_CACHED(uw)(MemoryRegionCache *cache,
30 assert(addr < cache->len && 2 <= cache->len - addr);
31 fuzz_dma_read_cb(cache->xlat + addr, 2, cache->mrs.mr);
32 if (likely(cache->ptr)) {
33 return LD_P(uw)(cache->ptr + addr);
35 return ADDRESS_SPACE_LD_CACHED_SLOW(uw)(cache, addr, attrs, result);
39 static inline uint32_t ADDRESS_SPACE_LD_CACHED(l)(MemoryRegionCache *cache,
42 assert(addr < cache->len && 4 <= cache->len - addr);
43 fuzz_dma_read_cb(cache->xlat + addr, 4, cache->mrs.mr);
44 if (likely(cache->ptr)) {
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| /qemu/contrib/plugins/ |
| H A D | cache.c | 37 * A CacheSet is a set of cache blocks. A memory block that maps to a set can be
43 * whether a block is in the cache or not by searching for its tag.
45 * In order to search for memory data in the cache, the set identifier and tag
81 } Cache; typedef
92 void (*update_hit)(Cache *cache, int set, int blk);
93 void (*update_miss)(Cache *cache, int set, int blk);
95 void (*metadata_init)(Cache *cache);
96 void (*metadata_destroy)(Cache *cache);
99 static Cache **l1_dcaches, **l1_icaches;
102 static Cache **l2_ucaches;
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| /qemu/docs/ |
| H A D | qcow2-cache.txt | 1 qcow2 L2/refcount cache configuration
12 performance significantly. However, setting the right cache sizes is
50 an L2 cache in memory to speed up disk access.
52 The size of the L2 cache can be configured, and setting the right
73 QEMU keeps a refcount cache to speed up I/O much like the
74 aforementioned L2 cache, and its size can also be configured.
77 Choosing the right cache sizes
79 In order to choose the cache sizes we need to know how they relate to
100 For example, 1MB of L2 cache is needed to cover every 8 GB of the virtual
105 The refcount cache is 4 times the cluster size by default. With the default
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| H A D | xbzrle.txt | 15 be stored on the source. Those pages are stored in a dedicated cache
17 The larger the cache size the better the chances are that the page has already
18 been stored in the cache.
19 A small cache size will result in high cache miss rate.
20 Cache size can be changed before and during migration.
45 retrieving the old page content from the cache (default size of 64MB). The
74 Cache update strategy
76 Keeping the hot pages in the cache is effective for decreasing cache
78 increase after each ram dirty bitmap sync. When a cache conflict is
79 detected, XBZRLE will only evict pages in the cache that are older than
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| /qemu/block/ |
| H A D | qed-l2-cache.c | 2 * QEMU Enhanced Disk Format L2 Cache
15 * L2 table cache usage is as follows:
17 * An open image has one L2 table cache that is used to avoid accessing the
23 * table cache serves up recently referenced L2 tables.
25 * If there is a cache miss, that L2 table is read from the image file and
26 * committed to the cache. Subsequent accesses to that L2 table will be served
27 * from the cache until the table is evicted from the cache.
29 * L2 tables are also committed to the cache when new L2 tables are allocated
30 * in the image file. Since the L2 table cache is write-through, the new L2
32 * cache.
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| /qemu/qapi/ |
| H A D | machine-common.json | 55 # topology settings (e.g., cache topology), and this special
68 # combination of cache level and cache type.
70 # @l1d: L1 data cache.
72 # @l1i: L1 instruction cache.
74 # @l2: L2 (unified) cache.
76 # @l3: L3 (unified) cache
86 # Cache information for SMP system.
88 # @cache: Cache name, which is the combination of cache level
89 # and cache type.
91 # @topology: Cache topology level. It accepts the CPU topology
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| /qemu/tests/qemu-iotests/tests/ |
| H A D | block-status-cache | 4 # Test cases for the block-status cache.
61 Verify that the block-status cache is not corrupted by a
67 verify that the cache has not been corrupted.
85 # block-status cache.
86 # Due to a bug, this information did end up in the cache, though, and
91 # have the first sector in the cache, and so this will be served from
92 # the cache; and only the subsequent range will be queried from the
94 # cache.
96 # correct information: The first sector is not covered by the cache, so
98 # would return a data range, and this would then go into the cache,
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| /qemu/.gitlab-ci.d/ |
| H A D | windows.yml | 5 cache:
8 - msys64/var/cache
32 - If ( !(Test-Path -Path msys64\var\cache ) ) {
33 mkdir msys64\var\cache
38 - if ( Test-Path -Path msys64\var\cache\msys2.exe.sig ) {
40 …if ( ((Get-FileHash msys2.exe.sig).Hash -ne (Get-FileHash msys64\var\cache\msys2.exe.sig).Hash) ) {
42 Remove-Item -Path msys64\var\cache\msys2.exe.sig ;
43 if ( Test-Path -Path msys64\var\cache\msys2.exe ) {
44 Remove-Item -Path msys64\var\cache\msys2.exe
51 if ( Test-Path -Path msys64\var\cache\msys2.exe ) {
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| /qemu/include/hw/virtio/ |
| H A D | virtio-access.h | 160 MemoryRegionCache *cache, in virtio_lduw_phys_cached() argument
164 return lduw_be_phys_cached(cache, pa); in virtio_lduw_phys_cached()
166 return lduw_le_phys_cached(cache, pa); in virtio_lduw_phys_cached()
170 MemoryRegionCache *cache, in virtio_ldl_phys_cached() argument
174 return ldl_be_phys_cached(cache, pa); in virtio_ldl_phys_cached()
176 return ldl_le_phys_cached(cache, pa); in virtio_ldl_phys_cached()
180 MemoryRegionCache *cache, in virtio_ldq_phys_cached() argument
184 return ldq_be_phys_cached(cache, pa); in virtio_ldq_phys_cached()
186 return ldq_le_phys_cached(cache, pa); in virtio_ldq_phys_cached()
190 MemoryRegionCache *cache, in virtio_stw_phys_cached() argument
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| /qemu/hw/core/ |
| H A D | machine-smp.c | 296 if (test_bit(node->value->cache, caches_bitmap)) { in machine_parse_smp_cache()
298 "Invalid cache properties: %s. " in machine_parse_smp_cache()
299 "The cache properties are duplicated", in machine_parse_smp_cache()
300 CacheLevelAndType_str(node->value->cache)); in machine_parse_smp_cache()
304 machine_set_cache_topo_level(ms, node->value->cache, in machine_parse_smp_cache()
306 set_bit(node->value->cache, caches_bitmap); in machine_parse_smp_cache()
313 * Reject non "default" topology level if the cache isn't in machine_parse_smp_cache()
317 !mc->smp_props.cache_supported[props->cache]) { in machine_parse_smp_cache()
319 "%s cache topology not supported by this machine", in machine_parse_smp_cache()
320 CacheLevelAndType_str(props->cache)); in machine_parse_smp_cache()
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| /qemu/target/sparc/ |
| H A D | asi.h | 31 /* VAC Cache flushing on sun4c and sun4 */
51 #define ASI_M_TXTC_TAG 0x0C /* Instruction Cache Tag; rw, ss */
52 #define ASI_M_TXTC_DATA 0x0D /* Instruction Cache Data; rw, ss */
53 #define ASI_M_DATAC_TAG 0x0E /* Data Cache Tag; rw, ss */
54 #define ASI_M_DATAC_DATA 0x0F /* Data Cache Data; rw, ss */
56 /* The following cache flushing ASIs work only with the 'sta'
62 #define ASI_M_FLUSH_PAGE 0x10 /* Flush I&D Cache Line (page); wo, ss */
63 #define ASI_M_FLUSH_SEG 0x11 /* Flush I&D Cache Line (seg); wo, ss */
64 #define ASI_M_FLUSH_REGION 0x12 /* Flush I&D Cache Line (region); wo, ss */
65 #define ASI_M_FLUSH_CTX 0x13 /* Flush I&D Cache Line (context); wo, ss */
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