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/kvm-unit-tests/lib/arm/asm/
H A Dassembler.h15 * dcache_line_size - get the minimum D-cache line size from the CTR register
21 and \tmp, \tmp, #0xf // cache line size encoding
23 mov \reg, \reg, lsl \tmp // actual cache line size
27 * Macro to perform a data cache maintenance for the interval
H A Dsysreg.h26 #define CR_RR (1 << 14) /* Round Robin cache replacement */
/kvm-unit-tests/lib/arm64/asm/
H A Dassembler.h19 * raw_dcache_line_size - get the minimum D-cache line size on this CPU
24 ubfx \tmp, \tmp, #16, #4 // cache line size encoding
26 lsl \reg, \reg, \tmp // actual cache line size
30 * Macro to perform a data cache maintenance for the interval
/kvm-unit-tests/arm/
H A Dunittests.cfg267 # Cache emulation tests
268 [cache]
269 file = cache.flat
271 groups = cache
H A DMakefile.arm6463 tests += $(TEST_DIR)/cache.$(exe)
/kvm-unit-tests/
H A D.travis.yml3 cache: ccache
H A D.gitlab-ci.yml32 cache
92 cache
/kvm-unit-tests/x86/
H A Dmemory.c2 * Test for x86 cache and memory instructions
H A Dcet.c102 /* Flush the paging cache. */ in main()
H A Ddebug.c435 * Generate a bus lock (via a locked access that splits cache lines) in bus_lock_test()
H A Dpmu.c815 * a warm-up state to warm up the cache, it leads to the measured cycles in warm_up()
/kvm-unit-tests/lib/ppc64/asm/
H A Dpgtable-hwdef.h48 #define _PAGE_TOLERANT 0x00030 /* tolerant memory, cache inhibited */
/kvm-unit-tests/lib/x86/
H A Dio.c118 * The kernel sets PTEs for an ioremap() with page cache disabled, in ioremap()
/kvm-unit-tests/lib/powerpc/
H A Dsetup.c81 "i-cache-line-size", NULL); in cpu_set()
87 "d-cache-line-size", NULL); in cpu_set()
/kvm-unit-tests/powerpc/
H A Dcstart64.S85 /* copy a cache line size */