1b5f659beSAlexandru Elisei /* SPDX-License-Identifier: GPL-2.0-only */ 2b5f659beSAlexandru Elisei /* 3b5f659beSAlexandru Elisei * Based on the file arch/arm64/include/asm/assembled.h from Linux v5.10, which 4b5f659beSAlexandru Elisei * in turn is based on arch/arm/include/asm/assembler.h and 5b5f659beSAlexandru Elisei * arch/arm/mm/proc-macros.S 6b5f659beSAlexandru Elisei * 7b5f659beSAlexandru Elisei * Copyright (C) 1996-2000 Russell King 8b5f659beSAlexandru Elisei * Copyright (C) 2012 ARM Ltd. 9b5f659beSAlexandru Elisei */ 10b5f659beSAlexandru Elisei 11*0cc3a351SSean Christopherson #ifndef __ASSEMBLER__ 12b5f659beSAlexandru Elisei #error "Only include this from assembly code" 13b5f659beSAlexandru Elisei #endif 14b5f659beSAlexandru Elisei 1516f52ec9SCornelia Huck #ifndef _ASMARM64_ASSEMBLER_H_ 1616f52ec9SCornelia Huck #define _ASMARM64_ASSEMBLER_H_ 17b5f659beSAlexandru Elisei 18b5f659beSAlexandru Elisei /* 19b5f659beSAlexandru Elisei * raw_dcache_line_size - get the minimum D-cache line size on this CPU 20b5f659beSAlexandru Elisei * from the CTR register. 21b5f659beSAlexandru Elisei */ 22b5f659beSAlexandru Elisei .macro raw_dcache_line_size, reg, tmp 23b5f659beSAlexandru Elisei mrs \tmp, ctr_el0 // read CTR 24b5f659beSAlexandru Elisei ubfx \tmp, \tmp, #16, #4 // cache line size encoding 25b5f659beSAlexandru Elisei mov \reg, #4 // bytes per word 26b5f659beSAlexandru Elisei lsl \reg, \reg, \tmp // actual cache line size 27b5f659beSAlexandru Elisei .endm 28b5f659beSAlexandru Elisei 29b5f659beSAlexandru Elisei /* 30b5f659beSAlexandru Elisei * Macro to perform a data cache maintenance for the interval 31b5f659beSAlexandru Elisei * [addr, addr + size). Use the raw value for the dcache line size because 32b5f659beSAlexandru Elisei * kvm-unit-tests has no concept of scheduling. 33b5f659beSAlexandru Elisei * 34b5f659beSAlexandru Elisei * op: operation passed to dc instruction 357a84b7b2SThomas Huth * domain: domain used in dsb instruction 36b5f659beSAlexandru Elisei * addr: starting virtual address of the region 37b5f659beSAlexandru Elisei * size: size of the region 38b5f659beSAlexandru Elisei * Corrupts: addr, size, tmp1, tmp2 39b5f659beSAlexandru Elisei */ 40b5f659beSAlexandru Elisei 41b5f659beSAlexandru Elisei .macro dcache_by_line_op op, domain, addr, size, tmp1, tmp2 42b5f659beSAlexandru Elisei raw_dcache_line_size \tmp1, \tmp2 43b5f659beSAlexandru Elisei add \size, \addr, \size 44b5f659beSAlexandru Elisei sub \tmp2, \tmp1, #1 45b5f659beSAlexandru Elisei bic \addr, \addr, \tmp2 46b5f659beSAlexandru Elisei 9998: 47b5f659beSAlexandru Elisei dc \op, \addr 48b5f659beSAlexandru Elisei add \addr, \addr, \tmp1 49b5f659beSAlexandru Elisei cmp \addr, \size 50b5f659beSAlexandru Elisei b.lo 9998b 51b5f659beSAlexandru Elisei dsb \domain 52b5f659beSAlexandru Elisei .endm 53b5f659beSAlexandru Elisei 5416f52ec9SCornelia Huck #endif /* _ASMARM64_ASSEMBLER_H_ */ 55