Searched +full:bank +full:- +full:width (Results 1 – 22 of 22) sorted by relevance
5 * Copyright (C) 2024 Arnaud Minier <arnaud.minier@telecom-paris.fr>6 * Copyright (C) 2024 Inès Varhol <ines.varhol@telecom-paris.fr>8 * SPDX-License-Identifier: GPL-2.0-or-later115 const unsigned bank = (uintptr_t) opaque; in test_dm163_bank() local116 const int width = bank ? 192 : 144; in test_dm163_bank() local118 QTestState *qts = qtest_initf("-M b-l475e-iot01a"); in test_dm163_bank()123 GPIO_OUT(SELBK, bank); in test_dm163_bank()126 /* Fill bank with zeroes */ in test_dm163_bank()128 for (int i = 0; i < width; i++) { in test_dm163_bank()131 /* Fill bank with ones, check that we get the previous zeroes */ in test_dm163_bank()[all …]
22 * For now, this code can emulate flashes of 1, 2 or 4 bytes width.24 * - flash read25 * - flash write26 * - flash ID read27 * - sector erase28 * - CFI queries42 #include "hw/qdev-properties.h"43 #include "hw/qdev-properties-system.h"44 #include "system/block-backend.h"46 #include "qemu/error-report.h"[all …]
5 * Copyright (c) 2016-2019 BALATON Zoltan17 #include "hw/pci-host/ppc4xx.h"18 #include "hw/qdev-properties.h"40 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */60 /* single bank */72 MemoryRegion bank[4]; member91 ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE]; in dcr_read_l2sram()105 ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE]; in dcr_read_l2sram()129 /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/ in dcr_write_l2sram()143 /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/ in dcr_write_l2sram()[all …]
2 * QEMU PowerPC e500-based platforms20 #include "qemu/guest-random.h"24 #include "e500-ccsr.h"26 #include "qemu/config-file.h"28 #include "hw/char/serial-mm.h"30 #include "system/block-backend-io.h"40 #include "hw/qdev-properties.h"44 #include "qemu/host-utils.h"46 #include "hw/pci-host/ppce500.h"47 #include "qemu/error-report.h"[all …]
5 * SPDX-License-Identifier: GPL-2.0+8 /dts-v1/;11 #address-cells = <0x01>;12 #size-cells = <0x01>;23 stdout-path = "/plb/serial@84000000";27 #address-cells = <0x01>;28 #size-cells = <0x00>;32 clock-frequency = <0x3b9aca0>;33 compatible = "xlnx,microblaze-7.10.d";34 d-cache-baseaddr = <0x90000000>;[all …]
5 * SPDX-License-Identifier: GPL-2.0+8 /dts-v1/;11 #address-cells = < 0x01 >;12 #size-cells = < 0x01 >;22 ethernet0 = "/axi/axi-ethernet@82780000";28 stdout-path = "/axi/serial@83e00000";32 #address-cells = < 0x01 >;34 #size-cells = < 0x00 >;37 clock-frequency = < 0xbebc200 >;38 compatible = "xlnx,microblaze-8.10.a";[all …]
4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>11 /dts-v1/;14 #address-cells = <2>;15 #size-cells = <1>;18 dcr-parent = <&{/cpus/cpu@0}>;28 #address-cells = <1>;29 #size-cells = <0>;35 clock-frequency = <0>; /* Filled in by U-Boot */36 timebase-frequency = <0>; /* Filled in by U-Boot */37 i-cache-line-size = <32>;[all …]
43 #include "hw/qdev-properties.h"53 * - destination write mask support not complete (bits 5..7)54 * - optimize linear mappings55 * - optimize bitblt functions81 #define CIRRUS_MEMFLAGS_BANKSWITCH 0x80 // bank switching is enabled.147 // memory-mapped IO182 int width, int height);189 #define TYPE_PCI_CIRRUS_VGA "cirrus-vga"218 + ((int64_t)s->cirrus_blt_height - 1) * pitch in blit_region_is_unsafe()219 - s->cirrus_blt_width; in blit_region_is_unsafe()[all …]
10 #include "qemu/error-report.h"13 #include "hw/qdev-properties.h"45 if ((s->tmr & TMR_ORI) != 0 && (s->ter & TER_REF)) in m5206_timer_update()46 qemu_irq_raise(s->irq); in m5206_timer_update()48 qemu_irq_lower(s->irq); in m5206_timer_update()53 s->tmr = 0; in m5206_timer_reset()54 s->trr = 0; in m5206_timer_reset()62 ptimer_transaction_begin(s->timer); in m5206_timer_recalibrate()63 ptimer_stop(s->timer); in m5206_timer_recalibrate()65 if ((s->tmr & TMR_RST) == 0) { in m5206_timer_recalibrate()[all …]
37 #include "hw/char/serial-mm.h"38 #include "hw/qdev-properties.h"39 #include "system/address-spaces.h"49 #define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb"72 ram_addr_t ram_size = machine->ram_size; in petalogix_ml605_init()90 object_property_set_int(OBJECT(cpu), "use-fpu", 1, &error_abort); in petalogix_ml605_init()91 object_property_set_bool(OBJECT(cpu), "dcache-writeback", true, in petalogix_ml605_init()93 object_property_set_bool(OBJECT(cpu), "little-endian", true, &error_abort); in petalogix_ml605_init()106 /* 5th parameter 2 means bank-width in petalogix_ml605_init()107 * 10th parameter 0 means little-endian */ in petalogix_ml605_init()[all …]
1 /* SPDX-License-Identifier: GPL-2.0-or-later */6 #include "qemu/error-report.h"7 #include "qemu/guest-random.h"10 #include "hw/core/sysbus-fdt.h"14 #include "hw/pci-host/gpex.h"15 #include "hw/pci-host/ls7a.h"25 ms->fdt = create_device_tree(&lvms->fdt_size); in create_fdt()26 if (!ms->fdt) { in create_fdt()32 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", in create_fdt()33 "linux,dummy-loongson3"); in create_fdt()[all …]
2 * SH-7750 memory-mapped registers6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and43 * in 0x1f000000 - 0x1fffffff (area 7 address)55 /* Page Table Entry High register - PTEH */64 /* Page Table Entry Low register - PTEL */70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */[all …]
3 # allwinner-cpucfg.c8 # allwinner-h3-dramc.c18 # allwinner-r40-dramc.c22 …_dramc_offset_to_cell(uint64_t offset, int row, int bank, int col) "offset 0x%" PRIx64 " row %d ba…32 # allwinner-sid.c36 # allwinner-sramc.c70 empty_slot_write(uint64_t addr, unsigned width, uint64_t value, unsigned size, const char *name) "w…101 # mps2-scc.c108 # mps2-fpgaio.c113 # msf2-sysreg.c[all …]
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7 * COPYING file in the top-level directory.9 * SPDX-License-Identifier: GPL-v2-only14 #include "qemu/error-report.h"15 #include "qapi/qapi-commands-cxl.h"16 #include "hw/mem/memory-device.h"17 #include "hw/mem/pc-dimm.h"19 #include "hw/qdev-properties.h"20 #include "hw/qdev-properties-system.h"27 #include "qemu/guest-random.h"141 * NV: Reserved - the non volatile from DSMAS matters in ct3_build_cdat_entries_for_mr()[all …]
38 * further describe the buffer's format - for example tiling or compression.41 * ----------------55 * vendor-namespaced, and as such the relationship between a fourcc code and a57 * may preserve meaning - such as number of planes - from the fourcc code,63 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel75 * - Kernel and user-space drivers: for drivers it's important that modifiers79 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users92 * -----------------------97 * upstream in-kernel or open source userspace user does not apply.221 * IEEE 754-2008 binary16 half-precision float[all …]
2 * ARM mach-virt emulation23 * + we want to present a very stripped-down minimalist platform,41 #include "hw/vfio/vfio-calxeda-xgmac.h"42 #include "hw/vfio/vfio-amd-xgbe.h"57 #include "qemu/error-report.h"59 #include "hw/pci-host/gpex.h"60 #include "hw/virtio/virtio-pci.h"61 #include "hw/core/sysbus-fdt.h"62 #include "hw/platform-bus.h"63 #include "hw/qdev-properties.h"[all …]
2 * QEMU ARM CPU -- internal functions and types18 * <http://www.gnu.org/licenses/gpl-2.0.html>31 #include "accel/tcg/tb-cpu-state.h"33 #include "tcg/tcg-gvec-desc.h"36 #include "cpu-features.h"50 return EX_TBFLAG_ANY(env->hflags, MMUIDX); in arm_env_mmu_index()55 /* Return true if this exception number represents a QEMU-internal in excp_is_internal()73 * We will use the back-compat value:74 * - for QEMU CPU types added before we standardized on 1GHz75 * - for versioned machine types with a version of 9.0 or earlier[all …]
6 * SPDX-License-Identifier: GPL-2.0-or-later14 #include "cpu-features.h"15 #include "exec/page-protection.h"16 #include "exec/mmap-lock.h"17 #include "qemu/main-loop.h"20 #include "qemu/qemu-print.h"22 #include "exec/translation-block.h"24 #include "system/cpu-timers.h"29 #include "qemu/guest-random.h"33 #include "semihosting/common-semi.h"[all …]
2 * QEMU RISC-V VirtIO Board6 * RISC-V machine with 16550a UART and VirtIO MMIO23 #include "qemu/error-report.h"24 #include "qemu/guest-random.h"29 #include "hw/qdev-properties.h"30 #include "hw/char/serial-mm.h"32 #include "hw/core/sysbus-fdt.h"36 #include "hw/riscv/riscv-iommu-bits.h"46 #include "hw/platform-bus.h"55 #include "hw/pci-host/gpex.h"[all …]
14 "-h or -help display this help and exit\n", QEMU_ARCH_ALL)16 ``-h``21 "-version display version information and exit\n", QEMU_ARCH_ALL)23 ``-version``28 "-machine [type=]name[,prop[=value][,...]]\n"29 " selects emulated machine ('-machine help' for list)\n"33 " dump-guest-core=on|off include guest memory in a core dump (default=on)\n"34 " mem-merge=on|off controls memory merge support (default: on)\n"35 " aes-key-wrap=on|off controls support for AES key wrapping (default=on)\n"36 " dea-key-wrap=on|off controls support for DEA key wrapping (default=on)\n"[all …]
23 #include "qemu/qemu-print.h"24 #include "qemu/hw-version.h"26 #include "tcg/helper-tcg.h"27 #include "exec/translation-block.h"29 #include "hvf/hvf-i386.h"33 #include "qemu/error-report.h"34 #include "qapi/qapi-visit-machine.h"35 #include "standard-headers/asm-x86/kvm_para.h"36 #include "hw/qdev-properties.h"40 #include "confidential-guest.h"[all …]