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/linux-6.8/Documentation/arch/riscv/
Dhwprobe.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor,
25 have the same value. Otherwise -1 will be returned. For boolean-like keys, the
33 by sys_riscv_hwprobe() to only those which match each of the key-value pairs.
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Dpatch-acceptance.rst1 .. SPDX-License-Identifier: GPL-2.0
7 --------
8 The RISC-V instruction set architecture is developed in the open:
9 in-progress drafts are available for all to review and to experiment
11 during the development process - sometimes in ways that are
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
14 of churn, and the Linux development process prefers well-reviewed and
16 principles to the RISC-V-related code that will be accepted for
20 ---------
22 RISC-V has a patchwork instance, where the status of patches can be checked:
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Dboot.rst1 .. SPDX-License-Identifier: GPL-2.0
4 RISC-V Kernel Boot Requirements and Constraints
10 This document describes what the RISC-V kernel expects from bootloaders and
16 Pre-kernel Requirements and Constraints
19 The RISC-V kernel expects the following of bootloaders and platform firmware:
22 --------------
24 The RISC-V kernel expects:
30 ---------
32 The RISC-V kernel expects:
37 -------------------------------------
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Dvm-layout.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Virtual Memory Layout on RISC-V Linux
10 This document describes the virtual memory layout used by the RISC-V Linux
13 RISC-V Linux Kernel 32bit
16 RISC-V Linux Kernel SV32
17 ------------------------
21 RISC-V Linux Kernel 64bit
24 The RISC-V privileged architecture document states that the 64bit addresses
25 "must have bits 63–48 all equal to bit 47, or else a page-fault exception will
28 the RISC-V Linux Kernel resides.
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Dboot-image-header.rst2 Boot image header in RISC-V Linux
8 This document only describes the boot image header details for RISC-V Linux.
10 The following 64-byte header is present in decompressed Linux kernel image::
25 ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common
31 - This header is also reused to support EFI stub for RISC-V. EFI specification
37 - version field indicate header version number
47 - The "magic" field is deprecated as of version 0.2. In a future
52 - In current header, the flags field has only one field.
58 - Image size is mandatory for boot loader to load kernel image. Booting will
Dacpi.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ACPI on RISC-V
8 Conversion, 12/2022 of the RISC-V specifications, as defined by tag
9 "riscv-isa-release-1239329-2023-05-23" (commit 1239329
10 ) <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-1239329-2023-05-23>`_
Dvector.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Vector Extension Support for RISC-V Linux
8 order to support the use of the RISC-V Vector Extension.
11 ---------------------
15 these interfaces is to give init systems a way to modify the availability of V
19 are not portable to non-Linux, nor non-RISC-V environments, so it is discourage
20 to use in a portable code. To get the availability of V in an ELF program,
27 argument consists of two 2-bit enablement statuses and a bit for inheritance
30 Enablement status is a tri-state value each occupying 2-bit of space in
33 * :c:macro:`PR_RISCV_V_VSTATE_CTRL_DEFAULT`: Use the system-wide default
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/linux-6.8/Documentation/devicetree/bindings/timer/
Driscv,timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V timer
10 - Anup Patel <anup@brainfault.org>
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
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/linux-6.8/Documentation/devicetree/bindings/riscv/
Dextensions.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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/linux-6.8/Documentation/translations/it_IT/riscv/
Dpatch-acceptance.rst1 .. include:: ../disclaimer-ita.rst
3 :Original: :doc:`../../../arch/riscv/patch-acceptance`
10 ------------
12 L'insieme di istruzioni RISC-V sono sviluppate in modo aperto: le
15 dei nuovi moduli o estensioni possono cambiare in fase di sviluppo - a
18 supporto RISC-V nel kernel Linux. I manutentori Linux non amano
22 relativo all'architettura RISC-V che verrà accettato per l'inclusione
26 -------------------------------------------------------------------------
29 RISC-V li classifica come "Frozen" o "Retified". (Ovviamente, gli
33 In aggiunta, la specifica RISC-V permette agli implementatori di
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/linux-6.8/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
28 - #interrupt-cells : should be <1>. The interrupt sources are defined by the
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Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
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/linux-6.8/drivers/cpuidle/
DKconfig.riscv1 # SPDX-License-Identifier: GPL-2.0-only
3 # RISC-V CPU Idle drivers
7 bool "RISC-V SBI CPU idle Driver"
13 Select this option to enable RISC-V SBI firmware based CPU idle
14 driver for RISC-V systems. This drivers also supports hierarchical
/linux-6.8/Documentation/translations/zh_CN/arch/riscv/
Dvm-layout.rst1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../../disclaimer-zh_CN.rst
4 :Original: Documentation/arch/riscv/vm-layout.rst
12 RISC-V Linux上的虚拟内存布局
18 这份文件描述了RISC-V Linux内核使用的虚拟内存布局。
20 32位 RISC-V Linux 内核
23 RISC-V Linux Kernel SV32
24 ------------------------
28 64位 RISC-V Linux 内核
31 RISC-V特权架构文档指出，64位地址 "必须使第63-48位值都等于第47位，否则将发生缺页异常。"：这将虚
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Dpatch-acceptance.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_CN.rst
5 :Original: Documentation/arch/riscv/patch-acceptance.rst
11 .. _cn_riscv_patch-acceptance:
17 ----
18 RISC-V指令集体系结构是公开开发的：
20 生更改---有时以不兼容的方式对以前的草案进行更改。这种灵活性可能会给RISC-V Linux
22 们希望推广同样的规则到即将被内核合并的RISC-V相关代码。
25 ----------------
26 我们仅接受相关标准已经被RISC-V基金会标准为“已批准”或“已冻结”的扩展或模块的补丁。
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/linux-6.8/arch/riscv/
DKconfig.socs12 bool "Renesas RISC-V SoCs"
14 This enables support for the RISC-V based Renesas SoCs.
51 bool "T-HEAD RISC-V SoCs"
55 This enables support for the RISC-V based T-HEAD SoCs.
/linux-6.8/drivers/perf/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 If compiled as a module, it will be called arm-cci.
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
45 tristate "Arm CMN-600 PMU support"
48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh
56 Say y if you want to use CPU performance monitors on ARM-based
61 bool "RISC-V PMU framework"
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Driscv_pmu_legacy.c1 // SPDX-License-Identifier: GPL-2.0
3 * RISC-V performance counter support.
7 * This implementation is based on old RISC-V perf and ARM perf event code
22 struct perf_event_attr *attr = &event->attr; in pmu_legacy_ctr_get_idx()
24 if (event->attr.type != PERF_TYPE_HARDWARE) in pmu_legacy_ctr_get_idx()
25 return -EOPNOTSUPP; in pmu_legacy_ctr_get_idx()
26 if (attr->config == PERF_COUNT_HW_CPU_CYCLES) in pmu_legacy_ctr_get_idx()
28 else if (attr->config == PERF_COUNT_HW_INSTRUCTIONS) in pmu_legacy_ctr_get_idx()
31 return -EOPNOTSUPP; in pmu_legacy_ctr_get_idx()
48 struct hw_perf_event *hwc = &event->hw; in pmu_legacy_read_ctr()
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/linux-6.8/drivers/media/pci/cx88/
Dcx88-alsa.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include "cx88-reg.h"
22 #include <linux/dma-mapping.h>
37 chip->core->name, ##arg); \
41 * Data type declarations - Can be moded to a header file later
46 struct cx88_riscmem risc; member
81 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
115 struct cx88_audio_buffer *buf = chip->buf; in _cx88_start_audio_dma()
116 struct cx88_core *core = chip->core; in _cx88_start_audio_dma()
119 /* Make sure RISC/FIFO are off before changing FIFO/RISC settings */ in _cx88_start_audio_dma()
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/linux-6.8/drivers/irqchip/
Dirq-riscv-intc.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 SiFive
8 #define pr_fmt(fmt) "riscv-intc: " fmt
25 unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; in riscv_intc_irq()
34 * On RISC-V systems local interrupts are masked or unmasked by writing
42 csr_clear(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_mask()
47 csr_set(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_unmask()
53 * The RISC-V INTC driver uses handle_percpu_devid_irq() flow in riscv_intc_irq_eoi()
54 * for the per-HART local interrupts and child irqchip drivers in riscv_intc_irq_eoi()
56 * chained handlers for the per-HART local interrupts. in riscv_intc_irq_eoi()
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/linux-6.8/arch/riscv/kernel/
Dtime.c1 // SPDX-License-Identifier: GPL-2.0-only
29 if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop)) in time_init()
30 panic("RISC-V system with no 'timebase-frequency' in DTS\n"); in time_init()
38 panic("RISC-V ACPI system with no RHCT table\n"); in time_init()
40 riscv_timebase = rhct->time_base_freq; in time_init()
/linux-6.8/drivers/media/pci/cx23885/
Dcx23885-core.c1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include "altera-ci.h"
25 #include "cx23888-ir.h"
26 #include "cx23885-ir.h"
27 #include "cx23885-av.h"
28 #include "cx23885-input.h"
38 * encountered is "mpeg risc op code error". Only Ryzen platforms employ
45 …PARM_DESC(dma_reset_workaround, "periodic RiSC dma engine reset; 0-force disable, 1-driver detect …
51 static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
63 #define NO_SYNC_LINE (-1U)
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/linux-6.8/arch/riscv/include/asm/
Dacpi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013-2014, Linaro Ltd.
8 * Copyright (C) 2021-2023, Ventana Micro Systems Inc.
9 * Author: Sunil V L <sunilvl@ventanamicro.com>
25 #define acpi_strict 1 /* No out-of-spec workarounds on RISC-V */
53 * CPU will be always available in MADT on RISC-V.
81 return -EINVAL; in acpi_get_riscv_isa()
/linux-6.8/drivers/clocksource/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
180 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
203 32-bit free running decrementing counters.
238 bool "Integrator-AP timer driver" if COMPILE_TEST
241 Enables support for the Integrator-AP timer.
266 available on many OMAP-like platforms.
285 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
289 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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