1 // SPDX-License-Identifier: GPL-2.0
3  * RISC-V performance counter support.
7  * This implementation is based on old RISC-V perf and ARM perf event code
22 	struct perf_event_attr *attr = &event->attr;  in pmu_legacy_ctr_get_idx()
24 	if (event->attr.type != PERF_TYPE_HARDWARE)  in pmu_legacy_ctr_get_idx()
25 		return -EOPNOTSUPP;  in pmu_legacy_ctr_get_idx()
26 	if (attr->config == PERF_COUNT_HW_CPU_CYCLES)  in pmu_legacy_ctr_get_idx()
28 	else if (attr->config == PERF_COUNT_HW_INSTRUCTIONS)  in pmu_legacy_ctr_get_idx()
31 		return -EOPNOTSUPP;  in pmu_legacy_ctr_get_idx()
48 	struct hw_perf_event *hwc = &event->hw;  in pmu_legacy_read_ctr()
49 	int idx = hwc->idx;  in pmu_legacy_read_ctr()
68 	struct hw_perf_event *hwc = &event->hw;  in pmu_legacy_ctr_start()
77 	local64_set(&hwc->prev_count, initial_val);  in pmu_legacy_ctr_start()
82 	return event->hw.idx;  in pmu_legacy_csr_index()
87 	if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&  in pmu_legacy_event_mapped()
88 	    event->attr.config != PERF_COUNT_HW_INSTRUCTIONS)  in pmu_legacy_event_mapped()
91 	event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;  in pmu_legacy_event_mapped()
96 	if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES &&  in pmu_legacy_event_unmapped()
97 	    event->attr.config != PERF_COUNT_HW_INSTRUCTIONS)  in pmu_legacy_event_unmapped()
100 	event->hw.flags &= ~PERF_EVENT_FLAG_USER_READ_CNT;  in pmu_legacy_event_unmapped()
105  * compatible with new RISC-V PMU driver framework.
114 	pmu->cmask = BIT(RISCV_PMU_LEGACY_CYCLE) |  in pmu_legacy_init()
116 	pmu->ctr_start = pmu_legacy_ctr_start;  in pmu_legacy_init()
117 	pmu->ctr_stop = NULL;  in pmu_legacy_init()
118 	pmu->event_map = pmu_legacy_event_map;  in pmu_legacy_init()
119 	pmu->ctr_get_idx = pmu_legacy_ctr_get_idx;  in pmu_legacy_init()
120 	pmu->ctr_get_width = pmu_legacy_ctr_get_width;  in pmu_legacy_init()
121 	pmu->ctr_clear_idx = NULL;  in pmu_legacy_init()
122 	pmu->ctr_read = pmu_legacy_read_ctr;  in pmu_legacy_init()
123 	pmu->event_mapped = pmu_legacy_event_mapped;  in pmu_legacy_init()
124 	pmu->event_unmapped = pmu_legacy_event_unmapped;  in pmu_legacy_init()
125 	pmu->csr_index = pmu_legacy_csr_index;  in pmu_legacy_init()
126 	pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;  in pmu_legacy_init()
127 	pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;  in pmu_legacy_init()
129 	perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW);  in pmu_legacy_init()
138 		return -ENOMEM;  in pmu_legacy_device_probe()
163 	pdev = platform_device_register_simple(RISCV_PMU_LEGACY_PDEV_NAME, -1, NULL, 0);  in riscv_pmu_legacy_devinit()