Lines Matching +full:risc +full:- +full:v
1 // SPDX-License-Identifier: GPL-2.0-or-later
24 #include "altera-ci.h"
25 #include "cx23888-ir.h"
26 #include "cx23885-ir.h"
27 #include "cx23885-av.h"
28 #include "cx23885-input.h"
38 * encountered is "mpeg risc op code error". Only Ryzen platforms employ
45 …PARM_DESC(dma_reset_workaround, "periodic RiSC dma engine reset; 0-force disable, 1-driver detect …
51 static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
63 #define NO_SYNC_LINE (-1U)
310 spin_lock_irqsave(&dev->pci_irqmask_lock, flags); in cx23885_irq_add()
312 dev->pci_irqmask |= mask; in cx23885_irq_add()
314 spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags); in cx23885_irq_add()
320 spin_lock_irqsave(&dev->pci_irqmask_lock, flags); in cx23885_irq_add_enable()
322 dev->pci_irqmask |= mask; in cx23885_irq_add_enable()
325 spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags); in cx23885_irq_add_enable()
330 u32 v; in cx23885_irq_enable() local
332 spin_lock_irqsave(&dev->pci_irqmask_lock, flags); in cx23885_irq_enable()
334 v = mask & dev->pci_irqmask; in cx23885_irq_enable()
335 if (v) in cx23885_irq_enable()
336 cx_set(PCI_INT_MSK, v); in cx23885_irq_enable()
338 spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags); in cx23885_irq_enable()
349 spin_lock_irqsave(&dev->pci_irqmask_lock, flags); in cx23885_irq_disable()
353 spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags); in cx23885_irq_disable()
364 spin_lock_irqsave(&dev->pci_irqmask_lock, flags); in cx23885_irq_remove()
366 dev->pci_irqmask &= ~mask; in cx23885_irq_remove()
369 spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags); in cx23885_irq_remove()
374 u32 v; in cx23885_irq_get_mask() local
376 spin_lock_irqsave(&dev->pci_irqmask_lock, flags); in cx23885_irq_get_mask()
378 v = cx_read(PCI_INT_MSK); in cx23885_irq_get_mask()
380 spin_unlock_irqrestore(&dev->pci_irqmask_lock, flags); in cx23885_irq_get_mask()
381 return v; in cx23885_irq_get_mask()
384 static int cx23885_risc_decode(u32 risc) in cx23885_risc_decode() argument
415 printk(KERN_DEBUG "0x%08x [ %s", risc, in cx23885_risc_decode()
416 instr[risc >> 28] ? instr[risc >> 28] : "INVALID"); in cx23885_risc_decode()
417 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--) in cx23885_risc_decode()
418 if (risc & (1 << (i + 12))) in cx23885_risc_decode()
420 pr_cont(" count=%d ]\n", risc & 0xfff); in cx23885_risc_decode()
421 return incr[risc >> 28] ? incr[risc >> 28] : 1; in cx23885_risc_decode()
432 if (list_empty(&q->active)) in cx23885_wakeup()
434 buf = list_entry(q->active.next, in cx23885_wakeup()
437 buf->vb.vb2_buf.timestamp = ktime_get_ns(); in cx23885_wakeup()
438 buf->vb.sequence = q->count++; in cx23885_wakeup()
439 if (count != (q->count % 65536)) { in cx23885_wakeup()
441 buf->vb.vb2_buf.index, count, q->count); in cx23885_wakeup()
444 buf->vb.vb2_buf.index, count, q->count); in cx23885_wakeup()
446 list_del(&buf->queue); in cx23885_wakeup()
447 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); in cx23885_wakeup()
448 max_buf_done--; in cx23885_wakeup()
450 count_delta = ((int)count - (int)(q->count % 65536)); in cx23885_wakeup()
456 unsigned int bpl, u32 risc) in cx23885_sram_channel_setup() argument
461 if (ch->cmds_start == 0) { in cx23885_sram_channel_setup()
463 ch->name); in cx23885_sram_channel_setup()
464 cx_write(ch->ptr1_reg, 0); in cx23885_sram_channel_setup()
465 cx_write(ch->ptr2_reg, 0); in cx23885_sram_channel_setup()
466 cx_write(ch->cnt2_reg, 0); in cx23885_sram_channel_setup()
467 cx_write(ch->cnt1_reg, 0); in cx23885_sram_channel_setup()
471 ch->name); in cx23885_sram_channel_setup()
475 cdt = ch->cdt; in cx23885_sram_channel_setup()
476 lines = ch->fifo_size / bpl; in cx23885_sram_channel_setup()
487 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i, in cx23885_sram_channel_setup()
488 ch->fifo_start + bpl*i); in cx23885_sram_channel_setup()
489 cx_write(cdt + 16*i, ch->fifo_start + bpl*i); in cx23885_sram_channel_setup()
496 if (ch->jumponly) in cx23885_sram_channel_setup()
497 cx_write(ch->cmds_start + 0, 8); in cx23885_sram_channel_setup()
499 cx_write(ch->cmds_start + 0, risc); in cx23885_sram_channel_setup()
500 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */ in cx23885_sram_channel_setup()
501 cx_write(ch->cmds_start + 8, cdt); in cx23885_sram_channel_setup()
502 cx_write(ch->cmds_start + 12, (lines*16) >> 3); in cx23885_sram_channel_setup()
503 cx_write(ch->cmds_start + 16, ch->ctrl_start); in cx23885_sram_channel_setup()
504 if (ch->jumponly) in cx23885_sram_channel_setup()
505 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2)); in cx23885_sram_channel_setup()
507 cx_write(ch->cmds_start + 20, 64 >> 2); in cx23885_sram_channel_setup()
509 cx_write(ch->cmds_start + i, 0); in cx23885_sram_channel_setup()
512 cx_write(ch->ptr1_reg, ch->fifo_start); in cx23885_sram_channel_setup()
513 cx_write(ch->ptr2_reg, cdt); in cx23885_sram_channel_setup()
514 cx_write(ch->cnt2_reg, (lines*16) >> 3); in cx23885_sram_channel_setup()
515 cx_write(ch->cnt1_reg, (bpl >> 3) - 1); in cx23885_sram_channel_setup()
518 dev->bridge, in cx23885_sram_channel_setup()
519 ch->name, in cx23885_sram_channel_setup()
530 "init risc lo", in cx23885_sram_channel_dump()
531 "init risc hi", in cx23885_sram_channel_dump()
536 "risc pc lo", in cx23885_sram_channel_dump()
537 "risc pc hi", in cx23885_sram_channel_dump()
545 u32 risc; in cx23885_sram_channel_dump() local
548 pr_warn("%s: %s - dma channel status dump\n", in cx23885_sram_channel_dump()
549 dev->name, ch->name); in cx23885_sram_channel_dump()
551 pr_warn("%s: cmds: %-15s: 0x%08x\n", in cx23885_sram_channel_dump()
552 dev->name, name[i], in cx23885_sram_channel_dump()
553 cx_read(ch->cmds_start + 4*i)); in cx23885_sram_channel_dump()
556 risc = cx_read(ch->cmds_start + 4 * (i + 14)); in cx23885_sram_channel_dump()
557 pr_warn("%s: risc%d:", dev->name, i); in cx23885_sram_channel_dump()
558 cx23885_risc_decode(risc); in cx23885_sram_channel_dump()
561 risc = cx_read(ch->ctrl_start + 4 * i); in cx23885_sram_channel_dump()
562 /* No consideration for bits 63-32 */ in cx23885_sram_channel_dump()
564 pr_warn("%s: (0x%08x) iq %x:", dev->name, in cx23885_sram_channel_dump()
565 ch->ctrl_start + 4 * i, i); in cx23885_sram_channel_dump()
566 n = cx23885_risc_decode(risc); in cx23885_sram_channel_dump()
568 risc = cx_read(ch->ctrl_start + 4 * (i + j)); in cx23885_sram_channel_dump()
570 dev->name, i+j, risc, j); in cx23885_sram_channel_dump()
574 pr_warn("%s: fifo: 0x%08x -> 0x%x\n", in cx23885_sram_channel_dump()
575 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size); in cx23885_sram_channel_dump()
576 pr_warn("%s: ctrl: 0x%08x -> 0x%x\n", in cx23885_sram_channel_dump()
577 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16); in cx23885_sram_channel_dump()
579 dev->name, cx_read(ch->ptr1_reg)); in cx23885_sram_channel_dump()
581 dev->name, cx_read(ch->ptr2_reg)); in cx23885_sram_channel_dump()
583 dev->name, cx_read(ch->cnt1_reg)); in cx23885_sram_channel_dump()
585 dev->name, cx_read(ch->cnt2_reg)); in cx23885_sram_channel_dump()
589 struct cx23885_riscmem *risc) in cx23885_risc_disasm() argument
591 struct cx23885_dev *dev = port->dev; in cx23885_risc_disasm()
594 pr_info("%s: risc disasm: %p [dma=0x%08lx]\n", in cx23885_risc_disasm()
595 dev->name, risc->cpu, (unsigned long)risc->dma); in cx23885_risc_disasm()
596 for (i = 0; i < (risc->size >> 2); i += n) { in cx23885_risc_disasm()
597 pr_info("%s: %04d:", dev->name, i); in cx23885_risc_disasm()
598 n = cx23885_risc_decode(le32_to_cpu(risc->cpu[i])); in cx23885_risc_disasm()
601 dev->name, i + j, risc->cpu[i + j], j); in cx23885_risc_disasm()
602 if (risc->cpu[i] == cpu_to_le32(RISC_JUMP)) in cx23885_risc_disasm()
611 if (!dev->need_dma_reset) in cx23885_clear_bridge_error()
614 reg1_val = cx_read(TC_REQ); /* read-only */ in cx23885_clear_bridge_error()
625 dev_info(&dev->pci->dev, in cx23885_clear_bridge_error()
633 /* disable RISC controller */ in cx23885_shutdown()
680 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01], in cx23885_reset()
682 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0); in cx23885_reset()
683 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03], in cx23885_reset()
685 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0); in cx23885_reset()
686 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0); in cx23885_reset()
687 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06], in cx23885_reset()
689 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0); in cx23885_reset()
690 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0); in cx23885_reset()
691 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0); in cx23885_reset()
710 if (dev->bridge == CX23885_BRIDGE_885) in cx23885_pci_quirks()
720 if (request_mem_region(pci_resource_start(dev->pci, 0), in get_resources()
721 pci_resource_len(dev->pci, 0), in get_resources()
722 dev->name)) in get_resources()
726 dev->name, (unsigned long long)pci_resource_start(dev->pci, 0)); in get_resources()
728 return -EBUSY; in get_resources()
736 /* Transport bus init dma queue - Common settings */ in cx23885_init_tsport()
737 port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */ in cx23885_init_tsport()
738 port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */ in cx23885_init_tsport()
739 port->vld_misc_val = 0x0; in cx23885_init_tsport()
740 port->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4); in cx23885_init_tsport()
742 spin_lock_init(&port->slock); in cx23885_init_tsport()
743 port->dev = dev; in cx23885_init_tsport()
744 port->nr = portno; in cx23885_init_tsport()
746 INIT_LIST_HEAD(&port->mpegq.active); in cx23885_init_tsport()
747 mutex_init(&port->frontends.lock); in cx23885_init_tsport()
748 INIT_LIST_HEAD(&port->frontends.felist); in cx23885_init_tsport()
749 port->frontends.active_fe_id = 0; in cx23885_init_tsport()
752 * attachment to this tsport, keeping the -dvb.c in cx23885_init_tsport()
755 if (!port->num_frontends) in cx23885_init_tsport()
756 port->num_frontends = 1; in cx23885_init_tsport()
760 port->reg_gpcnt = VID_B_GPCNT; in cx23885_init_tsport()
761 port->reg_gpcnt_ctl = VID_B_GPCNT_CTL; in cx23885_init_tsport()
762 port->reg_dma_ctl = VID_B_DMA_CTL; in cx23885_init_tsport()
763 port->reg_lngth = VID_B_LNGTH; in cx23885_init_tsport()
764 port->reg_hw_sop_ctrl = VID_B_HW_SOP_CTL; in cx23885_init_tsport()
765 port->reg_gen_ctrl = VID_B_GEN_CTL; in cx23885_init_tsport()
766 port->reg_bd_pkt_status = VID_B_BD_PKT_STATUS; in cx23885_init_tsport()
767 port->reg_sop_status = VID_B_SOP_STATUS; in cx23885_init_tsport()
768 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT; in cx23885_init_tsport()
769 port->reg_vld_misc = VID_B_VLD_MISC; in cx23885_init_tsport()
770 port->reg_ts_clk_en = VID_B_TS_CLK_EN; in cx23885_init_tsport()
771 port->reg_src_sel = VID_B_SRC_SEL; in cx23885_init_tsport()
772 port->reg_ts_int_msk = VID_B_INT_MSK; in cx23885_init_tsport()
773 port->reg_ts_int_stat = VID_B_INT_STAT; in cx23885_init_tsport()
774 port->sram_chno = SRAM_CH03; /* VID_B */ in cx23885_init_tsport()
775 port->pci_irqmask = 0x02; /* VID_B bit1 */ in cx23885_init_tsport()
778 port->reg_gpcnt = VID_C_GPCNT; in cx23885_init_tsport()
779 port->reg_gpcnt_ctl = VID_C_GPCNT_CTL; in cx23885_init_tsport()
780 port->reg_dma_ctl = VID_C_DMA_CTL; in cx23885_init_tsport()
781 port->reg_lngth = VID_C_LNGTH; in cx23885_init_tsport()
782 port->reg_hw_sop_ctrl = VID_C_HW_SOP_CTL; in cx23885_init_tsport()
783 port->reg_gen_ctrl = VID_C_GEN_CTL; in cx23885_init_tsport()
784 port->reg_bd_pkt_status = VID_C_BD_PKT_STATUS; in cx23885_init_tsport()
785 port->reg_sop_status = VID_C_SOP_STATUS; in cx23885_init_tsport()
786 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT; in cx23885_init_tsport()
787 port->reg_vld_misc = VID_C_VLD_MISC; in cx23885_init_tsport()
788 port->reg_ts_clk_en = VID_C_TS_CLK_EN; in cx23885_init_tsport()
789 port->reg_src_sel = 0; in cx23885_init_tsport()
790 port->reg_ts_int_msk = VID_C_INT_MSK; in cx23885_init_tsport()
791 port->reg_ts_int_stat = VID_C_INT_STAT; in cx23885_init_tsport()
792 port->sram_chno = SRAM_CH06; /* VID_C */ in cx23885_init_tsport()
793 port->pci_irqmask = 0x04; /* VID_C bit2 */ in cx23885_init_tsport()
807 dev->hwrevision = 0xa0; in cx23885_dev_checkrevision()
810 /* CX23885-12Z */ in cx23885_dev_checkrevision()
811 dev->hwrevision = 0xa1; in cx23885_dev_checkrevision()
814 /* CX23885-13Z/14Z */ in cx23885_dev_checkrevision()
815 dev->hwrevision = 0xb0; in cx23885_dev_checkrevision()
818 if (dev->pci->device == 0x8880) { in cx23885_dev_checkrevision()
819 /* CX23888-21Z/22Z */ in cx23885_dev_checkrevision()
820 dev->hwrevision = 0xc0; in cx23885_dev_checkrevision()
822 /* CX23885-14Z */ in cx23885_dev_checkrevision()
823 dev->hwrevision = 0xa4; in cx23885_dev_checkrevision()
827 if (dev->pci->device == 0x8880) { in cx23885_dev_checkrevision()
828 /* CX23888-31Z */ in cx23885_dev_checkrevision()
829 dev->hwrevision = 0xd0; in cx23885_dev_checkrevision()
831 /* CX23885-15Z, CX23888-31Z */ in cx23885_dev_checkrevision()
832 dev->hwrevision = 0xa5; in cx23885_dev_checkrevision()
836 /* CX23887-15Z */ in cx23885_dev_checkrevision()
837 dev->hwrevision = 0xc0; in cx23885_dev_checkrevision()
840 /* CX23887-14Z */ in cx23885_dev_checkrevision()
841 dev->hwrevision = 0xb1; in cx23885_dev_checkrevision()
845 __func__, dev->hwrevision); in cx23885_dev_checkrevision()
847 if (dev->hwrevision) in cx23885_dev_checkrevision()
849 __func__, dev->hwrevision); in cx23885_dev_checkrevision()
852 __func__, dev->hwrevision); in cx23885_dev_checkrevision()
861 spin_lock(&dev->v4l2_dev.lock); in cx23885_find_hw()
862 v4l2_device_for_each_subdev(sd, &dev->v4l2_dev) { in cx23885_find_hw()
863 if (sd->grp_id == hw) { in cx23885_find_hw()
868 spin_unlock(&dev->v4l2_dev.lock); in cx23885_find_hw()
876 spin_lock_init(&dev->pci_irqmask_lock); in cx23885_dev_setup()
877 spin_lock_init(&dev->slock); in cx23885_dev_setup()
879 mutex_init(&dev->lock); in cx23885_dev_setup()
880 mutex_init(&dev->gpio_lock); in cx23885_dev_setup()
882 atomic_inc(&dev->refcount); in cx23885_dev_setup()
884 dev->nr = cx23885_devcount++; in cx23885_dev_setup()
885 sprintf(dev->name, "cx23885[%d]", dev->nr); in cx23885_dev_setup()
888 if (dev->pci->device == 0x8880) { in cx23885_dev_setup()
890 dev->bridge = CX23885_BRIDGE_888; in cx23885_dev_setup()
892 dev->clk_freq = 50000000; in cx23885_dev_setup()
893 dev->sram_channels = cx23887_sram_channels; in cx23885_dev_setup()
895 if (dev->pci->device == 0x8852) { in cx23885_dev_setup()
896 dev->bridge = CX23885_BRIDGE_885; in cx23885_dev_setup()
898 dev->clk_freq = 28000000; in cx23885_dev_setup()
899 dev->sram_channels = cx23885_sram_channels; in cx23885_dev_setup()
904 __func__, dev->bridge); in cx23885_dev_setup()
907 dev->board = UNSET; in cx23885_dev_setup()
908 if (card[dev->nr] < cx23885_bcount) in cx23885_dev_setup()
909 dev->board = card[dev->nr]; in cx23885_dev_setup()
910 for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++) in cx23885_dev_setup()
911 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor && in cx23885_dev_setup()
912 dev->pci->subsystem_device == cx23885_subids[i].subdevice) in cx23885_dev_setup()
913 dev->board = cx23885_subids[i].card; in cx23885_dev_setup()
914 if (UNSET == dev->board) { in cx23885_dev_setup()
915 dev->board = CX23885_BOARD_UNKNOWN; in cx23885_dev_setup()
919 if (dev->pci->device == 0x8852) { in cx23885_dev_setup()
921 if (dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC) in cx23885_dev_setup()
922 dev->board = CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885; in cx23885_dev_setup()
923 else if (dev->board == CX23885_BOARD_HAUPPAUGE_QUADHD_DVB) in cx23885_dev_setup()
924 dev->board = CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885; in cx23885_dev_setup()
928 if (cx23885_boards[dev->board].clk_freq > 0) in cx23885_dev_setup()
929 dev->clk_freq = cx23885_boards[dev->board].clk_freq; in cx23885_dev_setup()
931 if (dev->board == CX23885_BOARD_HAUPPAUGE_IMPACTVCBE && in cx23885_dev_setup()
932 dev->pci->subsystem_device == 0x7137) { in cx23885_dev_setup()
938 dev->clk_freq = 25000000; in cx23885_dev_setup()
941 dev->pci_bus = dev->pci->bus->number; in cx23885_dev_setup()
942 dev->pci_slot = PCI_SLOT(dev->pci->devfn); in cx23885_dev_setup()
946 dev->i2c_bus[0].nr = 0; in cx23885_dev_setup()
947 dev->i2c_bus[0].dev = dev; in cx23885_dev_setup()
948 dev->i2c_bus[0].reg_stat = I2C1_STAT; in cx23885_dev_setup()
949 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL; in cx23885_dev_setup()
950 dev->i2c_bus[0].reg_addr = I2C1_ADDR; in cx23885_dev_setup()
951 dev->i2c_bus[0].reg_rdata = I2C1_RDATA; in cx23885_dev_setup()
952 dev->i2c_bus[0].reg_wdata = I2C1_WDATA; in cx23885_dev_setup()
953 dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */ in cx23885_dev_setup()
956 dev->i2c_bus[1].nr = 1; in cx23885_dev_setup()
957 dev->i2c_bus[1].dev = dev; in cx23885_dev_setup()
958 dev->i2c_bus[1].reg_stat = I2C2_STAT; in cx23885_dev_setup()
959 dev->i2c_bus[1].reg_ctrl = I2C2_CTRL; in cx23885_dev_setup()
960 dev->i2c_bus[1].reg_addr = I2C2_ADDR; in cx23885_dev_setup()
961 dev->i2c_bus[1].reg_rdata = I2C2_RDATA; in cx23885_dev_setup()
962 dev->i2c_bus[1].reg_wdata = I2C2_WDATA; in cx23885_dev_setup()
963 dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */ in cx23885_dev_setup()
966 dev->i2c_bus[2].nr = 2; in cx23885_dev_setup()
967 dev->i2c_bus[2].dev = dev; in cx23885_dev_setup()
968 dev->i2c_bus[2].reg_stat = I2C3_STAT; in cx23885_dev_setup()
969 dev->i2c_bus[2].reg_ctrl = I2C3_CTRL; in cx23885_dev_setup()
970 dev->i2c_bus[2].reg_addr = I2C3_ADDR; in cx23885_dev_setup()
971 dev->i2c_bus[2].reg_rdata = I2C3_RDATA; in cx23885_dev_setup()
972 dev->i2c_bus[2].reg_wdata = I2C3_WDATA; in cx23885_dev_setup()
973 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */ in cx23885_dev_setup()
975 if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) || in cx23885_dev_setup()
976 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)) in cx23885_dev_setup()
977 cx23885_init_tsport(dev, &dev->ts1, 1); in cx23885_dev_setup()
979 if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) || in cx23885_dev_setup()
980 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)) in cx23885_dev_setup()
981 cx23885_init_tsport(dev, &dev->ts2, 2); in cx23885_dev_setup()
985 dev->name, dev->pci->subsystem_vendor, in cx23885_dev_setup()
986 dev->pci->subsystem_device); in cx23885_dev_setup()
988 cx23885_devcount--; in cx23885_dev_setup()
989 return -ENODEV; in cx23885_dev_setup()
993 dev->lmmio = ioremap(pci_resource_start(dev->pci, 0), in cx23885_dev_setup()
994 pci_resource_len(dev->pci, 0)); in cx23885_dev_setup()
996 dev->bmmio = (u8 __iomem *)dev->lmmio; in cx23885_dev_setup()
999 dev->name, dev->pci->subsystem_vendor, in cx23885_dev_setup()
1000 dev->pci->subsystem_device, cx23885_boards[dev->board].name, in cx23885_dev_setup()
1001 dev->board, card[dev->nr] == dev->board ? in cx23885_dev_setup()
1007 dev->tuner_type = cx23885_boards[dev->board].tuner_type; in cx23885_dev_setup()
1008 dev->tuner_addr = cx23885_boards[dev->board].tuner_addr; in cx23885_dev_setup()
1009 dev->tuner_bus = cx23885_boards[dev->board].tuner_bus; in cx23885_dev_setup()
1010 dev->radio_type = cx23885_boards[dev->board].radio_type; in cx23885_dev_setup()
1011 dev->radio_addr = cx23885_boards[dev->board].radio_addr; in cx23885_dev_setup()
1014 __func__, dev->tuner_type, dev->tuner_addr, dev->tuner_bus); in cx23885_dev_setup()
1016 __func__, dev->radio_type, dev->radio_addr); in cx23885_dev_setup()
1022 if ((cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) || in cx23885_dev_setup()
1023 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)) in cx23885_dev_setup()
1029 cx23885_i2c_register(&dev->i2c_bus[0]); in cx23885_dev_setup()
1030 cx23885_i2c_register(&dev->i2c_bus[1]); in cx23885_dev_setup()
1031 cx23885_i2c_register(&dev->i2c_bus[2]); in cx23885_dev_setup()
1036 if (dev->board == CX23885_BOARD_VIEWCAST_460E) { in cx23885_dev_setup()
1046 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) { in cx23885_dev_setup()
1053 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) { in cx23885_dev_setup()
1054 if (cx23885_boards[dev->board].num_fds_portb) in cx23885_dev_setup()
1055 dev->ts1.num_frontends = in cx23885_dev_setup()
1056 cx23885_boards[dev->board].num_fds_portb; in cx23885_dev_setup()
1057 if (cx23885_dvb_register(&dev->ts1) < 0) { in cx23885_dev_setup()
1062 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) { in cx23885_dev_setup()
1069 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) { in cx23885_dev_setup()
1070 if (cx23885_boards[dev->board].num_fds_portc) in cx23885_dev_setup()
1071 dev->ts2.num_frontends = in cx23885_dev_setup()
1072 cx23885_boards[dev->board].num_fds_portc; in cx23885_dev_setup()
1073 if (cx23885_dvb_register(&dev->ts2) < 0) { in cx23885_dev_setup()
1078 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) { in cx23885_dev_setup()
1088 if (cx23885_boards[dev->board].ci_type > 0) in cx23885_dev_setup()
1091 switch (dev->board) { in cx23885_dev_setup()
1103 release_mem_region(pci_resource_start(dev->pci, 0), in cx23885_dev_unregister()
1104 pci_resource_len(dev->pci, 0)); in cx23885_dev_unregister()
1106 if (!atomic_dec_and_test(&dev->refcount)) in cx23885_dev_unregister()
1109 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) in cx23885_dev_unregister()
1112 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) in cx23885_dev_unregister()
1113 cx23885_dvb_unregister(&dev->ts1); in cx23885_dev_unregister()
1115 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) in cx23885_dev_unregister()
1118 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) in cx23885_dev_unregister()
1119 cx23885_dvb_unregister(&dev->ts2); in cx23885_dev_unregister()
1121 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) in cx23885_dev_unregister()
1124 cx23885_i2c_unregister(&dev->i2c_bus[2]); in cx23885_dev_unregister()
1125 cx23885_i2c_unregister(&dev->i2c_bus[1]); in cx23885_dev_unregister()
1126 cx23885_i2c_unregister(&dev->i2c_bus[0]); in cx23885_dev_unregister()
1128 iounmap(dev->lmmio); in cx23885_dev_unregister()
1143 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ in cx23885_risc_field()
1154 offset -= sg_dma_len(sg); in cx23885_risc_field()
1163 if (bpl <= sg_dma_len(sg)-offset) { in cx23885_risc_field()
1167 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ in cx23885_risc_field()
1173 (sg_dma_len(sg)-offset)); in cx23885_risc_field()
1175 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ in cx23885_risc_field()
1176 todo -= (sg_dma_len(sg)-offset); in cx23885_risc_field()
1183 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ in cx23885_risc_field()
1184 todo -= sg_dma_len(sg); in cx23885_risc_field()
1189 *(rp++) = cpu_to_le32(0); /* bits 63-32 */ in cx23885_risc_field()
1198 int cx23885_risc_buffer(struct pci_dev *pci, struct cx23885_riscmem *risc, in cx23885_risc_buffer() argument
1212 /* estimate risc mem: worst case is one write per page border + in cx23885_risc_buffer()
1220 risc->size = instructions * 12; in cx23885_risc_buffer()
1221 risc->cpu = dma_alloc_coherent(&pci->dev, risc->size, &risc->dma, in cx23885_risc_buffer()
1223 if (risc->cpu == NULL) in cx23885_risc_buffer()
1224 return -ENOMEM; in cx23885_risc_buffer()
1226 /* write risc instructions */ in cx23885_risc_buffer()
1227 rp = risc->cpu; in cx23885_risc_buffer()
1236 risc->jmp = rp; in cx23885_risc_buffer()
1237 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); in cx23885_risc_buffer()
1242 struct cx23885_riscmem *risc, in cx23885_risc_databuffer() argument
1250 /* estimate risc mem: worst case is one write per page border + in cx23885_risc_databuffer()
1258 risc->size = instructions * 12; in cx23885_risc_databuffer()
1259 risc->cpu = dma_alloc_coherent(&pci->dev, risc->size, &risc->dma, in cx23885_risc_databuffer()
1261 if (risc->cpu == NULL) in cx23885_risc_databuffer()
1262 return -ENOMEM; in cx23885_risc_databuffer()
1264 /* write risc instructions */ in cx23885_risc_databuffer()
1265 rp = risc->cpu; in cx23885_risc_databuffer()
1270 risc->jmp = rp; in cx23885_risc_databuffer()
1271 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); in cx23885_risc_databuffer()
1275 int cx23885_risc_vbibuffer(struct pci_dev *pci, struct cx23885_riscmem *risc, in cx23885_risc_vbibuffer() argument
1289 /* estimate risc mem: worst case is one write per page border + in cx23885_risc_vbibuffer()
1297 risc->size = instructions * 12; in cx23885_risc_vbibuffer()
1298 risc->cpu = dma_alloc_coherent(&pci->dev, risc->size, &risc->dma, in cx23885_risc_vbibuffer()
1300 if (risc->cpu == NULL) in cx23885_risc_vbibuffer()
1301 return -ENOMEM; in cx23885_risc_vbibuffer()
1302 /* write risc instructions */ in cx23885_risc_vbibuffer()
1303 rp = risc->cpu; in cx23885_risc_vbibuffer()
1318 risc->jmp = rp; in cx23885_risc_vbibuffer()
1319 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof(*risc->cpu) > risc->size); in cx23885_risc_vbibuffer()
1326 struct cx23885_riscmem *risc = &buf->risc; in cx23885_free_buffer() local
1328 if (risc->cpu) in cx23885_free_buffer()
1329 dma_free_coherent(&dev->pci->dev, risc->size, risc->cpu, risc->dma); in cx23885_free_buffer()
1330 memset(risc, 0, sizeof(*risc)); in cx23885_free_buffer()
1335 struct cx23885_dev *dev = port->dev; in cx23885_tsport_reg_dump()
1357 port->reg_gpcnt, cx_read(port->reg_gpcnt)); in cx23885_tsport_reg_dump()
1359 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl)); in cx23885_tsport_reg_dump()
1361 port->reg_dma_ctl, cx_read(port->reg_dma_ctl)); in cx23885_tsport_reg_dump()
1362 if (port->reg_src_sel) in cx23885_tsport_reg_dump()
1364 port->reg_src_sel, cx_read(port->reg_src_sel)); in cx23885_tsport_reg_dump()
1366 port->reg_lngth, cx_read(port->reg_lngth)); in cx23885_tsport_reg_dump()
1368 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl)); in cx23885_tsport_reg_dump()
1370 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl)); in cx23885_tsport_reg_dump()
1372 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status)); in cx23885_tsport_reg_dump()
1374 port->reg_sop_status, cx_read(port->reg_sop_status)); in cx23885_tsport_reg_dump()
1376 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat)); in cx23885_tsport_reg_dump()
1378 port->reg_vld_misc, cx_read(port->reg_vld_misc)); in cx23885_tsport_reg_dump()
1380 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en)); in cx23885_tsport_reg_dump()
1382 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk)); in cx23885_tsport_reg_dump()
1384 port->reg_ts_int_stat, cx_read(port->reg_ts_int_stat)); in cx23885_tsport_reg_dump()
1401 struct cx23885_dev *dev = port->dev; in cx23885_start_dma()
1405 dev->width, dev->height, dev->field); in cx23885_start_dma()
1410 /* Stop the fifo and risc engine for this port */ in cx23885_start_dma()
1411 cx_clear(port->reg_dma_ctl, port->dma_ctl_val); in cx23885_start_dma()
1415 &dev->sram_channels[port->sram_chno], in cx23885_start_dma()
1416 port->ts_packet_size, buf->risc.dma); in cx23885_start_dma()
1419 &dev->sram_channels[port->sram_chno]); in cx23885_start_dma()
1420 cx23885_risc_disasm(port, &buf->risc); in cx23885_start_dma()
1424 cx_write(port->reg_lngth, port->ts_packet_size); in cx23885_start_dma()
1426 if ((!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) && in cx23885_start_dma()
1427 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB))) { in cx23885_start_dma()
1430 cx23885_boards[dev->board].portb, in cx23885_start_dma()
1431 cx23885_boards[dev->board].portc); in cx23885_start_dma()
1432 return -EINVAL; in cx23885_start_dma()
1435 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) in cx23885_start_dma()
1441 if (port->reg_src_sel) in cx23885_start_dma()
1442 cx_write(port->reg_src_sel, port->src_sel_val); in cx23885_start_dma()
1444 cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val); in cx23885_start_dma()
1445 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val); in cx23885_start_dma()
1446 cx_write(port->reg_vld_misc, port->vld_misc_val); in cx23885_start_dma()
1447 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val); in cx23885_start_dma()
1452 cx_write(port->reg_gpcnt_ctl, 3); in cx23885_start_dma()
1453 q->count = 0; in cx23885_start_dma()
1456 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) { in cx23885_start_dma()
1463 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) { in cx23885_start_dma()
1469 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) { in cx23885_start_dma()
1491 switch (dev->bridge) { in cx23885_start_dma()
1499 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val); in cx23885_start_dma()
1500 cx_set(port->reg_dma_ctl, port->dma_ctl_val); in cx23885_start_dma()
1504 cx23885_irq_add(dev, port->pci_irqmask); in cx23885_start_dma()
1514 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */ in cx23885_start_dma()
1518 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) in cx23885_start_dma()
1534 struct cx23885_dev *dev = port->dev; in cx23885_stop_dma()
1543 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val); in cx23885_stop_dma()
1544 cx_clear(port->reg_dma_ctl, port->dma_ctl_val); in cx23885_stop_dma()
1554 dev_dbg(&dev->pci->dev, "delay=%d reg1=0x%08x reg2=0x%08x\n", in cx23885_stop_dma()
1557 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) { in cx23885_stop_dma()
1566 cx_write(port->reg_src_sel, 0); in cx23885_stop_dma()
1567 cx_write(port->reg_gen_ctrl, 8); in cx23885_stop_dma()
1570 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) in cx23885_stop_dma()
1576 /* ------------------------------------------------------------------ */
1580 struct cx23885_dev *dev = port->dev; in cx23885_buf_prepare()
1581 int size = port->ts_packet_size * port->ts_packet_count; in cx23885_buf_prepare()
1582 struct sg_table *sgt = vb2_dma_sg_plane_desc(&buf->vb.vb2_buf, 0); in cx23885_buf_prepare()
1585 if (vb2_plane_size(&buf->vb.vb2_buf, 0) < size) in cx23885_buf_prepare()
1586 return -EINVAL; in cx23885_buf_prepare()
1587 vb2_set_plane_payload(&buf->vb.vb2_buf, 0, size); in cx23885_buf_prepare()
1589 cx23885_risc_databuffer(dev->pci, &buf->risc, in cx23885_buf_prepare()
1590 sgt->sgl, in cx23885_buf_prepare()
1591 port->ts_packet_size, port->ts_packet_count, 0); in cx23885_buf_prepare()
1596 * The risc program for each buffer works as follows: it starts with a simple
1601 * This is the risc program of the first buffer to be queued if the active list
1613 * The end-result of all this that you only get an interrupt when a buffer
1619 struct cx23885_dev *dev = port->dev; in cx23885_buf_queue()
1620 struct cx23885_dmaqueue *cx88q = &port->mpegq; in cx23885_buf_queue()
1623 buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12); in cx23885_buf_queue()
1624 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC); in cx23885_buf_queue()
1625 buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12); in cx23885_buf_queue()
1626 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ in cx23885_buf_queue()
1628 spin_lock_irqsave(&dev->slock, flags); in cx23885_buf_queue()
1629 if (list_empty(&cx88q->active)) { in cx23885_buf_queue()
1630 list_add_tail(&buf->queue, &cx88q->active); in cx23885_buf_queue()
1631 dprintk(1, "[%p/%d] %s - first active\n", in cx23885_buf_queue()
1632 buf, buf->vb.vb2_buf.index, __func__); in cx23885_buf_queue()
1634 buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1); in cx23885_buf_queue()
1635 prev = list_entry(cx88q->active.prev, struct cx23885_buffer, in cx23885_buf_queue()
1637 list_add_tail(&buf->queue, &cx88q->active); in cx23885_buf_queue()
1638 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); in cx23885_buf_queue()
1639 dprintk(1, "[%p/%d] %s - append to active\n", in cx23885_buf_queue()
1640 buf, buf->vb.vb2_buf.index, __func__); in cx23885_buf_queue()
1642 spin_unlock_irqrestore(&dev->slock, flags); in cx23885_buf_queue()
1645 /* ----------------------------------------------------------- */
1649 struct cx23885_dmaqueue *q = &port->mpegq; in do_cancel_buffers()
1653 spin_lock_irqsave(&port->slock, flags); in do_cancel_buffers()
1654 while (!list_empty(&q->active)) { in do_cancel_buffers()
1655 buf = list_entry(q->active.next, struct cx23885_buffer, in do_cancel_buffers()
1657 list_del(&buf->queue); in do_cancel_buffers()
1658 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); in do_cancel_buffers()
1659 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n", in do_cancel_buffers()
1660 buf, buf->vb.vb2_buf.index, reason, in do_cancel_buffers()
1661 (unsigned long)buf->risc.dma); in do_cancel_buffers()
1663 spin_unlock_irqrestore(&port->slock, flags); in do_cancel_buffers()
1676 struct cx23885_tsport *port = &dev->ts1; in cx23885_irq_417()
1683 count = cx_read(port->reg_gpcnt); in cx23885_irq_417()
1685 status, cx_read(port->reg_ts_int_msk), count); in cx23885_irq_417()
1694 pr_err("%s: V4L mpeg risc op code error, status = 0x%x\n", in cx23885_irq_417()
1695 dev->name, status); in cx23885_irq_417()
1711 cx_clear(port->reg_dma_ctl, port->dma_ctl_val); in cx23885_irq_417()
1713 &dev->sram_channels[port->sram_chno]); in cx23885_irq_417()
1717 spin_lock(&port->slock); in cx23885_irq_417()
1718 cx23885_wakeup(port, &port->mpegq, count); in cx23885_irq_417()
1719 spin_unlock(&port->slock); in cx23885_irq_417()
1722 cx_write(port->reg_ts_int_stat, status); in cx23885_irq_417()
1731 struct cx23885_dev *dev = port->dev; in cx23885_irq_ts()
1756 pr_err("%s: mpeg risc op code error\n", dev->name); in cx23885_irq_ts()
1758 cx_clear(port->reg_dma_ctl, port->dma_ctl_val); in cx23885_irq_ts()
1760 &dev->sram_channels[port->sram_chno]); in cx23885_irq_ts()
1766 spin_lock(&port->slock); in cx23885_irq_ts()
1767 count = cx_read(port->reg_gpcnt); in cx23885_irq_ts()
1768 cx23885_wakeup(port, &port->mpegq, count); in cx23885_irq_ts()
1769 spin_unlock(&port->slock); in cx23885_irq_ts()
1773 cx_write(port->reg_ts_int_stat, status); in cx23885_irq_ts()
1783 struct cx23885_tsport *ts1 = &dev->ts1; in cx23885_irq()
1784 struct cx23885_tsport *ts2 = &dev->ts2; in cx23885_irq()
1818 ts1_count = cx_read(ts1->reg_gpcnt); in cx23885_irq()
1819 ts2_count = cx_read(ts2->reg_gpcnt); in cx23885_irq()
1895 if (cx23885_boards[dev->board].ci_type == 1 && in cx23885_irq()
1899 if (cx23885_boards[dev->board].ci_type == 2 && in cx23885_irq()
1904 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) in cx23885_irq()
1907 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) in cx23885_irq()
1912 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) in cx23885_irq()
1915 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) in cx23885_irq()
1927 v4l2_subdev_call(dev->sd_ir, core, interrupt_service_routine, in cx23885_irq()
1935 schedule_work(&dev->cx25840_work); in cx23885_irq()
1953 dev = to_cx23885(sd->v4l2_dev); in cx23885_v4l2_dev_notify()
1957 if (sd == dev->sd_ir) in cx23885_v4l2_dev_notify()
1961 if (sd == dev->sd_ir) in cx23885_v4l2_dev_notify()
1969 INIT_WORK(&dev->cx25840_work, cx23885_av_work_handler); in cx23885_v4l2_dev_notify_init()
1970 INIT_WORK(&dev->ir_rx_work, cx23885_ir_rx_work_handler); in cx23885_v4l2_dev_notify_init()
1971 INIT_WORK(&dev->ir_tx_work, cx23885_ir_tx_work_handler); in cx23885_v4l2_dev_notify_init()
1972 dev->v4l2_dev.notify = cx23885_v4l2_dev_notify; in cx23885_v4l2_dev_notify_init()
1977 return cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER; in encoder_on_portb()
1982 return cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER; in encoder_on_portc()
1993 * GPIO 2 through 0 - On the cx23885 bridge
1994 * GPIO 18 through 3 - On the cx23417 host bus interface
1995 * GPIO 23 through 19 - On the cx25840 a/v core
2005 dev->name); in cx23885_gpio_set()
2009 /* TODO: 23-19 */ in cx23885_gpio_set()
2011 pr_info("%s: Unsupported\n", dev->name); in cx23885_gpio_set()
2022 dev->name); in cx23885_gpio_clear()
2026 /* TODO: 23-19 */ in cx23885_gpio_clear()
2028 pr_info("%s: Unsupported\n", dev->name); in cx23885_gpio_clear()
2039 dev->name); in cx23885_gpio_get()
2043 /* TODO: 23-19 */ in cx23885_gpio_get()
2045 pr_info("%s: Unsupported\n", dev->name); in cx23885_gpio_get()
2060 dev->name); in cx23885_gpio_enable()
2070 /* TODO: 23-19 */ in cx23885_gpio_enable()
2077 * https://openbenchmarking.org/system/1703021-RI-AMDZEN08075/Ryzen%207%201800X/lspci,
2081 /* According to sudo lspci -nn,
2088 /* 0x1419 is the PCI ID for the IOMMU found on 15h (Models 10h-1fh) family
2129 return -ENOMEM; in cx23885_initdev()
2131 dev->need_dma_reset = cx23885_does_need_dma_reset(); in cx23885_initdev()
2133 err = v4l2_device_register(&pci_dev->dev, &dev->v4l2_dev); in cx23885_initdev()
2137 hdl = &dev->ctrl_handler; in cx23885_initdev()
2139 if (hdl->error) { in cx23885_initdev()
2140 err = hdl->error; in cx23885_initdev()
2143 dev->v4l2_dev.ctrl_handler = hdl; in cx23885_initdev()
2149 dev->pci = pci_dev; in cx23885_initdev()
2151 err = -EIO; in cx23885_initdev()
2156 err = -EINVAL; in cx23885_initdev()
2161 dev->pci_rev = pci_dev->revision; in cx23885_initdev()
2162 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat); in cx23885_initdev()
2164 dev->name, in cx23885_initdev()
2165 pci_name(pci_dev), dev->pci_rev, pci_dev->irq, in cx23885_initdev()
2166 dev->pci_lat, in cx23885_initdev()
2170 err = dma_set_mask(&pci_dev->dev, 0xffffffff); in cx23885_initdev()
2172 pr_err("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name); in cx23885_initdev()
2176 err = request_irq(pci_dev->irq, cx23885_irq, in cx23885_initdev()
2177 IRQF_SHARED, dev->name, dev); in cx23885_initdev()
2180 dev->name, pci_dev->irq); in cx23885_initdev()
2184 switch (dev->board) { in cx23885_initdev()
2207 v4l2_device_unregister(&dev->v4l2_dev); in cx23885_initdev()
2224 free_irq(pci_dev->irq, dev); in cx23885_finidev()
2229 v4l2_ctrl_handler_free(&dev->ctrl_handler); in cx23885_finidev()
2248 /* --- end of list --- */