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/qemu/include/hw/misc/
H A Dnpcm7xx_pwm.h2 * Nuvoton NPCM7xx PWM Module
23 /* Each PWM module holds 4 PWM channels. */
27 * Number of registers in one pwm module. Don't change this without increasing
34 * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
35 * value of 100,000 the duty cycle for that PWM is 10%.
42 * struct NPCM7xxPWM - The state of a single PWM channel.
43 * @module: The PWM module that contains this channel.
45 * @running: Whether this PWM channel is generating output.
46 * @inverted: Whether this PWM channel is inverted.
47 * @index: The index of this PWM channel.
[all …]
/qemu/tests/qtest/
H A Dnpcm7xx_pwm-test.c2 * QTests for Nuvoton NPCM7xx PWM Modules.
58 /* MFT (PWM fan) related */
106 typedef struct PWM { struct
111 } PWM; argument
115 const PWM *pwm; member
129 static const PWM pwm_list[] = {
201 /* Returns the index of the PWM module. */
211 /* Returns the index of the PWM entry. */
212 static int pwm_index(const PWM *pwm) in pwm_index() argument
214 ptrdiff_t diff = pwm - pwm_list; in pwm_index()
[all …]
/qemu/hw/misc/
H A Dnpcm7xx_pwm.c2 * Nuvoton NPCM7xx PWM Module
64 /* Offset of each PWM channel's prescaler in the PPR register. */
66 /* Offset of each PWM channel's clock selector in the CSR register. */
68 /* Offset of each PWM channel's control variable in the PCR register. */
161 npcm7xx_pwm_update_freq(&s->pwm[i]); in npcm7xx_pwm_write_ppr()
175 npcm7xx_pwm_update_freq(&s->pwm[i]); in npcm7xx_pwm_write_csr()
190 p = &s->pwm[i]; in npcm7xx_pwm_write_pcr()
195 * We only run a PWM channel with toggle mode. Single-shot mode does not in npcm7xx_pwm_write_pcr()
200 /* Re-run this PWM channel if inverted changed. */ in npcm7xx_pwm_write_pcr()
206 /* Run this PWM channel. */ in npcm7xx_pwm_write_pcr()
[all …]
/qemu/hw/timer/
H A Dexynos4210_pwm.c39 do { fprintf(stdout, "PWM: [%24s:%5d] " fmt, __func__, __LINE__, \
105 #define TYPE_EXYNOS4210_PWM "exynos4210.pwm"
123 .name = "exynos4210.pwm.pwm",
137 .name = "exynos4210.pwm",
152 * PWM update frequency.
217 * PWM Read
260 "exynos4210.pwm: bad read offset " HWADDR_FMT_plx, in exynos4210_pwm_read()
268 * PWM Write
355 "exynos4210.pwm: bad write offset " HWADDR_FMT_plx, in exynos4210_pwm_write()
391 * PWM timer initialization
[all …]
H A Dstellaris-gptm.c48 /* PWM mode. Not implemented. */ in gptm_reload()
92 /* PWM mode. Not implemented. */ in gptm_tick()
H A Davr_timer16.c31 * PWM modes, GPIO, output capture pins, input compare pin
91 /* Timer mode values (not including PWM modes) */
218 qemu_log_mask(LOG_UNIMP, "%s: pwm modes are unsupported\n", in avr_timer16_set_alarm()
/qemu/include/hw/arm/
H A Dnpcm8xx.h60 * PWM fan splitter. each splitter connects to one PWM output and
93 NPCM7xxPWMState pwm[NPCM8XX_NR_PWM_MODULES]; member
H A Dnpcm7xx.h60 * PWM fan splitter. each splitter connects to one PWM output and
96 NPCM7xxPWMState pwm[NPCM7XX_NR_PWM_MODULES]; member
H A Dfsl-imx25.h134 * 0x53FA_0000 0x53FA_3FFF 16 Kbytes PWM-2
136 * 0x53FA_8000 0x53FA_BFFF 16 Kbytes PWM-3
144 * 0x53FC_8000 0x53FC_BFFF 16 Kbytes PWM-4
150 * 0x53FE_0000 0x53FE_3FFF 16 Kbytes PWM-1
H A Daspeed_soc.h99 UnimplementedDeviceState pwm; member
/qemu/include/hw/gpio/
H A Dpca9552_regs.h18 #define PCA9552_PWM0 3 /* read/write PWM register 0 */
20 #define PCA9552_PWM1 5 /* read/write PWM register 1 */
/qemu/include/hw/timer/
H A Dsifive_pwm.h2 * SiFive PWM
34 #define TYPE_SIFIVE_PWM "sifive-pwm"
/qemu/hw/arm/
H A Dnpcm8xx_boards.c106 * PWM 0~3 belong to module 0 output 0~3. in npcm8xx_init_pwm_splitter()
107 * PWM 4~7 belong to module 1 output 0~3. in npcm8xx_init_pwm_splitter()
123 qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out", in npcm8xx_init_pwm_splitter()
153 /* Connect the Fan to PWM module */ in npcm8xx_connect_pwm_fan()
H A Dnpcm7xx.c131 NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
132 NPCM7XX_PWM1_IRQ, /* PWM module 1 */
185 /* Register base address for each PWM Module */
457 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { in npcm7xx_init()
458 object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM); in npcm7xx_init()
646 /* PWM Modules. Cannot fail. */ in npcm7xx_realize()
647 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm)); in npcm7xx_realize()
648 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { in npcm7xx_realize()
649 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]); in npcm7xx_realize()
651 qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out( in npcm7xx_realize()
H A Dnpcm8xx.c119 NPCM8XX_PWM0_IRQ = 93, /* PWM module 0 */
120 NPCM8XX_PWM1_IRQ, /* PWM module 1 */
220 /* Register base address for each PWM Module */
455 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { in npcm8xx_init()
456 object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM); in npcm8xx_init()
667 /* PWM Modules. Cannot fail. */ in npcm8xx_realize()
668 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm8xx_pwm_addr) != ARRAY_SIZE(s->pwm)); in npcm8xx_realize()
669 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) { in npcm8xx_realize()
670 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]); in npcm8xx_realize()
672 qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out( in npcm8xx_realize()
H A Dmusca.c74 UnimplementedDeviceState pwm[3]; member
329 { "pwm0", make_unimp_dev, &mms->pwm[0], 0x7000, 0x1000 }, in make_musca_a_devs()
334 { "pwm1", make_unimp_dev, &mms->pwm[1], 0xe000, 0x1000 }, in make_musca_a_devs()
335 { "pwm2", make_unimp_dev, &mms->pwm[2], 0xf000, 0x1000 }, in make_musca_a_devs()
484 { "pwm0", make_unimp_dev, &mms->pwm[0], 0x40101000, 0x1000 }, in musca_init()
485 { "pwm1", make_unimp_dev, &mms->pwm[1], 0x40102000, 0x1000 }, in musca_init()
486 { "pwm2", make_unimp_dev, &mms->pwm[2], 0x40103000, 0x1000 }, in musca_init()
H A Dnpcm7xx_boards.c145 * PWM 0~3 belong to module 0 output 0~3. in npcm7xx_init_pwm_splitter()
146 * PWM 4~7 belong to module 1 output 0~3. in npcm7xx_init_pwm_splitter()
162 qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out", in npcm7xx_init_pwm_splitter()
192 /* Connect the Fan to PWM module */ in npcm7xx_connect_pwm_fan()
H A Daspeed_ast10x0.c177 object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE); in aspeed_soc_ast1030_init()
401 aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm", in aspeed_soc_ast1030_realize()
H A Dexynos4210.c43 /* PWM */
675 /* PWM */ in exynos4210_realize()
676 sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, in exynos4210_realize()
/qemu/hw/riscv/
H A Dsifive_u.c437 nodename = g_strdup_printf("/soc/pwm@%lx", in create_fdt()
450 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); in create_fdt()
453 nodename = g_strdup_printf("/soc/pwm@%lx", in create_fdt()
466 qemu_fdt_setprop_cell(fdt, nodename, "#pwm-cells", 0); in create_fdt()
780 object_initialize_child(obj, "pwm0", &s->pwm[0], TYPE_SIFIVE_PWM); in type_init()
781 object_initialize_child(obj, "pwm1", &s->pwm[1], TYPE_SIFIVE_PWM); in type_init()
907 /* PWM */ in sifive_u_soc_realize()
909 if (!sysbus_realize(SYS_BUS_DEVICE(&s->pwm[i]), errp)) { in sifive_u_soc_realize()
912 sysbus_mmio_map(SYS_BUS_DEVICE(&s->pwm[i]), 0, in sifive_u_soc_realize()
915 /* Connect PWM interrupts to the PLIC */ in sifive_u_soc_realize()
[all …]
/qemu/docs/system/arm/
H A Dmusca.rst15 - PWM
H A Draspi.rst43 * Pulse Width Modulation (PWM)
H A Daspeed.rst76 * PWM and Fan Controller
289 * PWM and Fan Controller
457 * PWM and Fan Controller
H A Dnuvoton.rst54 * Pulse Width Modulation (PWM)
/qemu/include/hw/riscv/
H A Dsifive_u.h55 SiFivePwmState pwm[2]; member

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