| /linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | gen7_renderclear.c | 1 // SPDX-License-Identifier: MIT
13 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
53 bv->max_primitives = 280; in batch_get_defaults()
54 bv->max_urb_entries = MAX_URB_ENTRIES; in batch_get_defaults()
55 bv->surface_height = 16 * 16; in batch_get_defaults()
56 bv->surface_width = 32 * 2 * 16; in batch_get_defaults()
58 bv->max_primitives = 128; in batch_get_defaults()
59 bv->max_urb_entries = MAX_URB_ENTRIES / 2; in batch_get_defaults()
60 bv->surface_height = 16 * 8; in batch_get_defaults()
61 bv->surface_width = 32 * 16; in batch_get_defaults()
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| D | gen6_engine_cs.c | 1 // SPDX-License-Identifier: MIT
17 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
19 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
21 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
22 * produced by non-pipelined state commands), software needs to first
23 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
26 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
27 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
31 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
32 * BEFORE the pipe-control with a post-sync op and no write-cache
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| D | selftest_lrc.c | 2 * SPDX-License-Identifier: MIT
24 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4)
34 obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in create_scratch()
40 vma = i915_vma_instance(obj, >->ggtt->vm, NULL); in create_scratch()
82 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
86 return -ETIME; in wait_for_submit()
89 } while (1); in wait_for_submit()
102 if (READ_ONCE(engine->execlists.pending[0])) in wait_for_reset()
108 if (READ_ONCE(rq->fence.error)) in wait_for_reset()
114 if (rq->fence.error != -EIO) { in wait_for_reset()
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| /linux-5.10/drivers/memory/ |
| D | stm32-fmc2-ebi.c | 1 // SPDX-License-Identifier: GPL-2.0
30 #define FMC2_BCR_MUXEN BIT(1)
99 FMC2_REG_BCR = 1,
146 * struct stm32_fmc2_prop - STM32 FMC2 EBI property
170 const struct stm32_fmc2_prop *prop, int cs);
171 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
174 int cs, u32 setup);
179 int cs) in stm32_fmc2_ebi_check_mux() argument
183 regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); in stm32_fmc2_ebi_check_mux()
188 return -EINVAL; in stm32_fmc2_ebi_check_mux()
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| D | omap-gpmc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2006 Nokia Corporation
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
30 #include <linux/omap-gpmc.h>
34 #include <linux/platform_data/mtd-nand-omap2.h>
36 #define DEVICE_NAME "omap-gpmc"
78 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
94 * The first 1MB of GPMC address space is typically mapped to
135 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
136 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
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| /linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | ti-aemif.txt | 4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
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| D | st,stm32-fmc2-ebi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
22 - Christophe Kerello <christophe.kerello@st.com>
26 const: st,stm32mp1-fmc2-ebi
29 maxItems: 1
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| /linux-5.10/drivers/scsi/ |
| D | myrs.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * This driver supports the newer, SCSI-based firmware interface only.
10 * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
91 * myrs_reset_cmd - clears critical fields in struct myrs_cmdblk
95 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_reset_cmd()
98 cmd_blk->status = 0; in myrs_reset_cmd()
102 * myrs_qcmd - queues Command for DAC960 V2 Series Controllers.
104 static void myrs_qcmd(struct myrs_hba *cs, struct myrs_cmdblk *cmd_blk) in myrs_qcmd() argument
106 void __iomem *base = cs->io_base; in myrs_qcmd()
107 union myrs_cmd_mbox *mbox = &cmd_blk->mbox; in myrs_qcmd()
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| /linux-5.10/kernel/time/ |
| D | clocksource.c | 1 // SPDX-License-Identifier: GPL-2.0+
18 #include "tick-internal.h"
22 * clocks_calc_mult_shift - calculate mult/shift factors for scaled math of clocks
33 * NSEC_PER_SEC == 1GHz and @from is the counter frequency. For clock
56 tmp >>=1; in clocks_calc_mult_shift()
57 sftacc--; in clocks_calc_mult_shift()
64 for (sft = 32; sft > 0; sft--) { in clocks_calc_mult_shift()
76 /*[Clocksource internal variables]---------
86 * Name of the user-specified clocksource.
119 static void __clocksource_change_rating(struct clocksource *cs, int rating);
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| /linux-5.10/include/linux/mfd/syscon/ |
| D | atmel-smc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
18 #define ATMEL_SMC_SETUP(cs) (((cs) * 0x10)) argument
19 #define ATMEL_HSMC_SETUP(layout, cs) \ argument
20 ((layout)->timing_regs_offset + ((cs) * 0x14))
21 #define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4) argument
22 #define ATMEL_HSMC_PULSE(layout, cs) \ argument
23 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
24 #define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8) argument
25 #define ATMEL_HSMC_CYCLE(layout, cs) \ argument
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| /linux-5.10/arch/m68k/include/asm/ |
| D | m5307sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
39 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
59 #define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */
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| D | m5407sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
39 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
58 #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
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| D | m5206sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
26 #define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
58 #define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
59 #define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
60 #define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
62 #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
63 #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
64 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
65 #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
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| /linux-5.10/fs/fuse/ |
| D | dev.c | 3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
29 #define FUSE_INT_REQ_BIT (1ULL << 0)
30 #define FUSE_REQ_ID_STEP (1ULL << 1)
37 * Lockless access is OK, because file->private data is set in fuse_get_dev()
40 return READ_ONCE(file->private_data); in fuse_get_dev()
45 INIT_LIST_HEAD(&req->list); in fuse_request_init()
46 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
47 init_waitqueue_head(&req->waitq); in fuse_request_init()
48 refcount_set(&req->count, 1); in fuse_request_init()
49 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
[all …]
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| /linux-5.10/drivers/staging/kpc2000/ |
| D | kpc2000_spi.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2014-2018 Daktronics
7 * Very loosely based on spi-omap2-mcspi.c
13 #include <linux/io-64-nonatomic-lo-hi.h>
63 .bus_num = 1,
70 .bus_num = 1,
71 .chip_select = 1,
91 #define KP_SPI_REG_CONFIG_TRM_RX 1
119 unsigned int pha : 1; /* spim_clk Phase */
120 unsigned int pol : 1; /* spim_clk Polarity */
[all …]
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| /linux-5.10/drivers/misc/habanalabs/common/ |
| D | command_submission.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2019 HabanaLabs, Ltd.
25 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset()
27 hdev->asic_funcs->reset_sob(hdev, hw_sob); in hl_sob_reset()
34 struct hl_device *hdev = hw_sob->hdev; in hl_sob_reset_error()
36 dev_crit(hdev->dev, in hl_sob_reset_error()
38 hw_sob->q_idx, hw_sob->sob_id); in hl_sob_reset_error()
47 struct hl_device *hdev = hl_cs_cmpl->hdev; in hl_fence_release()
49 /* EBUSY means the CS was never submitted and hence we don't have in hl_fence_release()
52 if (fence->error == -EBUSY) in hl_fence_release()
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| /linux-5.10/drivers/mfd/ |
| D | atmel-smc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
11 #include <linux/mfd/syscon/atmel-smc.h>
15 * atmel_smc_cs_conf_init - initialize a SMC CS conf
16 * @conf: the SMC CS conf to initialize
27 * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
40 * If the @ncycles value is too big to be encoded, -ERANGE is returned and
49 unsigned int lsbmask = GENMASK(msbpos - 1, 0); in atmel_smc_cs_encode_ncycles()
50 unsigned int msbmask = GENMASK(msbwidth - 1, 0); in atmel_smc_cs_encode_ncycles()
65 * We still return -ERANGE in case the caller cares. in atmel_smc_cs_encode_ncycles()
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| /linux-5.10/drivers/spi/ |
| D | spi-fsl-spi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
19 #include <linux/dma-mapping.h>
45 #include "spi-fsl-lib.h"
46 #include "spi-fsl-cpm.h"
47 #include "spi-fsl-spi.h"
50 #define TYPE_GRLIB 1
81 if (dev->of_node) { in fsl_spi_get_type()
82 match = of_match_node(of_fsl_spi_match, dev->of_node); in fsl_spi_get_type()
83 if (match && match->data) in fsl_spi_get_type()
84 return ((struct fsl_spi_match_data *)match->data)->type; in fsl_spi_get_type()
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| D | spi-omap2-mcspi.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/dma-mapping.h>
30 #include <linux/platform_data/spi-omap2-mcspi.h>
47 /* per-channel banks, 0x14 bytes each, first is: */
54 /* per-register bitmasks: */
62 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
81 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
90 /* We have 2 DMA channels per CS, one for RX and one for TX */
115 struct list_head cs; member
130 unsigned int pin_dir:1;
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| /linux-5.10/arch/mips/netlogic/xlr/ |
| D | platform-flash.c | 72 .name = "physmap-flash",
88 int cs; member
99 FLASH_NAND_CLE(nand_priv.cs), cmd); in xlr_nand_ctrl()
102 FLASH_NAND_ALE(nand_priv.cs), cmd); in xlr_nand_ctrl()
107 .nr_chips = 1,
125 .id = -1,
143 uint64_t flash_map_base, int cs, struct resource *res) in setup_flash_resource() argument
147 base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs)); in setup_flash_resource()
148 mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs)); in setup_flash_resource()
150 res->start = flash_map_base + ((unsigned long)base << 16); in setup_flash_resource()
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| /linux-5.10/drivers/net/slip/ |
| D | slhc.c | 21 * - Initial distribution.
28 * - 01-31-90 initial adaptation (from 1.19)
29 * PPP.05 02-15-90 [ks]
30 * PPP.08 05-02-90 [ks] use PPP protocol field to signal compression
31 * PPP.15 09-90 [ks] improve mbuf handling
32 * PPP.16 11-02 [karn] substantially rewritten to use NOS facilities
34 * - Feb 1991 Bill_Simpson@um.cc.umich.edu
39 * - Jul 1994 Dmitry Gorodchanin
41 * - Oct 1994 Dmitry Gorodchanin
43 * - Jan 1995 Bjorn Ekwall
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| /linux-5.10/kernel/cgroup/ |
| D | cpuset.c | 7 * Copyright (C) 2004-2007 Silicon Graphics, Inc.
11 * sysfs is Copyright (c) 2001-3 Patrick Mochel
13 * 2003-10-10 Written by Simon Derr.
14 * 2003-10-22 Updates by Stephen Hemminger.
15 * 2004 May-July Rework by Paul Jackson.
59 #include <linux/backing-dev.h>
89 * The user-configured masks can only be changed by writing to
103 * The user-configured masks are always the same with effective masks.
106 /* user-configured CPUs and Memory Nodes allow to tasks */
115 * CPUs allocated to child sub-partitions (default hierarchy only)
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| /linux-5.10/drivers/s390/char/ |
| D | raw3270.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
44 #define TF_INMDT 0xc1 /* Visible, Set-MDT */
55 /* Extended-Highlighting Bytes */
80 #define RAW3270_FIRSTMINOR 1 /* First minor number */
123 return list_empty(&rq->list); in raw3270_request_final()
153 #define RAW3270_VIEW_LOCK_BH 1
159 unsigned char *ascebc; /* ascii -> ebcdic table */
178 atomic_inc(&view->ref_count); in raw3270_get_view()
186 if (atomic_dec_return(&view->ref_count) == 0) in raw3270_put_view()
219 struct string *cs, *tmp; in alloc_string() local
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| /linux-5.10/include/linux/ |
| D | clocksource.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
34 * struct clocksource - hardware abstraction for a free running counter
35 * Provides mostly state-free accessors to the underlying hardware.
45 * @archdata: Optional arch-specific data
54 * 1-99: Unfit for real use
56 * 100-199: Base level usability.
58 * 200-299: Good.
60 * 300-399: Desired.
62 * 400-499: Perfect
63 * The ideal clocksource. A must-use where
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| /linux-5.10/drivers/clocksource/ |
| D | em_sti.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Emma Mobile Timer Support - STI
33 struct clocksource cs; member
55 return ioread32(p->base + offs); in em_sti_read()
61 iowrite32(value, p->base + offs); in em_sti_write()
69 ret = clk_enable(p->clk); in em_sti_enable()
71 dev_err(&p->pdev->dev, "cannot enable clock\n"); in em_sti_enable()
84 em_sti_write(p, STI_CONTROL, 1); in em_sti_enable()
95 clk_disable(p->clk); in em_sti_disable()
103 /* the STI hardware buffers the 48-bit count, but to in em_sti_count()
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