72 	.name	= "physmap-flash",
88 	int cs;  member
99 			FLASH_NAND_CLE(nand_priv.cs), cmd);  in xlr_nand_ctrl()
102 			FLASH_NAND_ALE(nand_priv.cs), cmd);  in xlr_nand_ctrl()
107 		.nr_chips	= 1,
125 	.id		= -1,
143 	uint64_t flash_map_base, int cs, struct resource *res)  in setup_flash_resource()  argument
147 	base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs));  in setup_flash_resource()
148 	mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs));  in setup_flash_resource()
150 	res->start = flash_map_base + ((unsigned long)base << 16);  in setup_flash_resource()
151 	res->end = res->start + (mask + 1) * 64 * 1024;  in setup_flash_resource()
158 	int cs, boot_nand, boot_nor;  in xlr_flash_init()  local
174 		if (gpio_resetcfg & (1 << 16))  in xlr_flash_init()
175 			boot_nand = 1;  in xlr_flash_init()
178 		if ((gpio_resetcfg & (1 << 15)) == 0)  in xlr_flash_init()
179 			boot_nor = 1;	/* not set, booted from NOR */  in xlr_flash_init()
182 		if ((gpio_resetcfg & (1 << 16)) == 0)  in xlr_flash_init()
183 			boot_nor = 1;	/* not set, booted from NOR */  in xlr_flash_init()
187 	cs = 0;  in xlr_flash_init()
190 		nand_priv.cs = cs;  in xlr_flash_init()
192 		setup_flash_resource(flash_mmio, flash_map_base, cs,  in xlr_flash_init()
195 		/* Initialize NAND flash at CS 0 */  in xlr_flash_init()
196 		nlm_write_reg(flash_mmio, FLASH_CSDEV_PARM(cs),  in xlr_flash_init()
198 		nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMA(cs),  in xlr_flash_init()
200 		nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMB(cs),  in xlr_flash_init()
203 		pr_info("ChipSelect %d: NAND Flash %pR\n", cs, xlr_nand_res);  in xlr_flash_init()
208 		setup_flash_resource(flash_mmio, flash_map_base, cs,  in xlr_flash_init()
210 		pr_info("ChipSelect %d: NOR Flash %pR\n", cs, xlr_nor_res);  in xlr_flash_init()