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/qemu/tests/qemu-iotests/
H A D1776 # Copyright (C) 2016-2018 Red Hat, Inc.
54 $QEMU_IO -c "write -P 11 0 $size" "$TEST_IMG.base" | _filter_qemu_io
55 _make_test_img -b "$TEST_IMG.base" -F $IMGFMT
56 $QEMU_IO -c "write -P 22 0 $size" "$TEST_IMG" | _filter_qemu_io
58 # Limited to 64k max-transfer
60 echo "== constrained alignment and max-transfer =="
61 limits=align=4k,max-transfer=64k
62 $QEMU_IO -c "open -o $options,$limits blkdebug::$TEST_IMG" \
63 -c "write -P 33 1000 128k" -c "read -P 33 1000 128k" | _filter_qemu_io
66 echo "== write zero with constrained max-transfer =="
[all …]
H A D2046 # Copyright (C) 2016-2018 Red Hat, Inc.
55 $QEMU_IO -c "write -P 11 0 $size" "$TEST_IMG.base" | _filter_qemu_io
56 _make_test_img -b "$TEST_IMG.base" -F $IMGFMT
57 $QEMU_IO -c "write -P 22 0 110M" "$TEST_IMG" | _filter_qemu_io
59 # Limited to 64k max-transfer
61 echo "== constrained alignment and max-transfer =="
62 limits=align=4k,max-transfer=64k
63 $QEMU_IO -c "open -o $options,$limits blkdebug::$TEST_IMG" \
64 -c "write -P 33 1000 128k" -c "read -P 33 1000 128k" | _filter_qemu_io
67 echo "== write zero with constrained max-transfer =="
[all …]
H A D0246 # Copyright (C) 2009 Red Hat, Inc.
57 # Backing (old) 11 -- 11 -- 11 -- 11 --
58 # Backing (new) 22 22 -- -- 22 22 -- --
59 # COW image 33 33 33 33 -- -- -- --
61 # The pattern is written twice to have both an alloc -> non-alloc and a
62 # non-alloc -> alloc transition in the COW image.
87 _make_test_img -b "$TEST_IMG.base_old" -F $IMGFMT 1G
113 $QEMU_IMG rebase -b "$TEST_IMG.base_new" -F $IMGFMT "$TEST_IMG"
154 # Backing (old): 11 11 -- 11
155 # Backing (new): -- 22 22 11
[all …]
H A D2526 # Copyright (C) 2019 Red Hat, Inc.
57 # Backing (new) 11 -- 11 -- 11 --
58 # COW image 22 22 11 11 -- --
62 # COW image 22 22 11 11 00 --
64 # (Cluster 2 might be "--" after the rebase, too, but rebase just
74 -c "write -P 0x22 $((0 * CLUSTER_SIZE)) $((2 * CLUSTER_SIZE))" \
75 -c "write -P 0x11 $((2 * CLUSTER_SIZE)) $((2 * CLUSTER_SIZE))" \
79 -c "write -P 0x11 $((0 * CLUSTER_SIZE)) $CLUSTER_SIZE" \
80 -c "write -P 0x11 $((2 * CLUSTER_SIZE)) $CLUSTER_SIZE" \
81 -c "write -P 0x11 $((4 * CLUSTER_SIZE)) $CLUSTER_SIZE" \
[all …]
H A D2076 # Copyright (C) 2018 Red Hat, Inc.
35 if key == 'hash' and re.match('[0-9a-f]+', value):
40 p = r"\S+ (key fingerprint) '(md5|sha1|sha256):[0-9a-f]+'"
65 'port': '22'
76 # Test host-key-check options
78 iotests.log("=== Test host-key-check options ===")
81 iotests.log("--- no host key checking --")
90 'port': '22'
92 'host-key-check': {
101 iotests.log("--- known_hosts key checking --")
[all …]
H A D271.out8 write -q -P PATTERN 0 1k
10 write -q -P PATTERN 3k 512
12 write -q -P PATTERN 5k 1k
14 write -q -P PATTERN 6k 2k
16 write -q -P PATTERN 8k 6k
18 write -q -P PATTERN 15k 4k
20 write -q -P PATTERN 32k 1k
22 write -q -P PATTERN 63k 4k
25 write -q -z 2k 2k
27 write -q -z 0 64k
[all …]
/qemu/hw/nvram/
H A Dxlnx-zynqmp-efuse.c4 * Copyright (c) 2015 Xilinx Inc.
5 * Copyright (c) 2023 Advanced Micro Devices, Inc.
29 #include "hw/nvram/xlnx-zynqmp-efuse.h"
34 #include "hw/qdev-properties.h"
203 * ZynqMP: UG1085 (v2.1) August 21, 2019, p.277, Table 12-13
205 #define EFUSE_AES_RDLK BIT_POS(22, 0)
206 #define EFUSE_AES_WRLK BIT_POS(22, 1)
207 #define EFUSE_ENC_ONLY BIT_POS(22, 2)
208 #define EFUSE_BBRAM_DIS BIT_POS(22, 3)
209 #define EFUSE_ERROR_DIS BIT_POS(22, 4)
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/qemu/linux-user/hppa/
H A Dvdso.S6 * SPDX-License-Identifier: GPL-2.0-or-later
10 #include "vdso-asmoffset.h"
18 * a 64-byte boundary by 0, 4 or 5 instructions. Since the vdso trampoline
28 /* arch/parisc/kernel/asm-offsets.c */
30 (offsetof_sigcontext - PARISC_RT_SIGFRAME_SIZE32)
54 .cfi_def_cfa 30, -PARISC_RT_SIGFRAME_SIZE32 + offsetof_sigcontext
78 .cfi_offset 22, offsetof_sigcontext_gr + 22 * 4
126 .cfi_offset 68, offsetof_sigcontext_fr + 22 * 8
127 .cfi_offset 69, offsetof_sigcontext_fr + 22 * 8 + 4
163 .size __kernel_sigtramp_rt, . - __kernel_sigtramp_rt
/qemu/target/arm/tcg/
H A Dm-nocp.decode1 # M-profile UserFault.NOCP exception handling
3 # Copyright (c) 2020 Linaro, Ltd
21 # For M-profile, the architecture specifies that NOCP UsageFaults
23 # range of coprocessor-space encodings, with the exception of
32 %vd_dp 22:1 12:4
33 %vd_sp 12:4 22:1
37 # M-profile VLDR/VSTR to sysreg
38 %vldr_sysreg 22:1 13:3
60 VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000
63 VLDR_sysreg ---- 110 1 . . w:1 1 .... ... 0 111 11 ....... @vldr_sysreg p=1
[all …]
H A Dvfp-uncond.decode3 # Copyright (c) 2019 Linaro, Ltd
30 # VFP registers have an odd encoding with a four-bit field
31 # and a one-bit field which are assembled in different orders
36 # support D16-D31" (which should UNDEF).
41 %vd_dp 22:1 12:4
42 %vd_sp 12:4 22:1
70 # VCVT float to int with specified rounding mode; Vd is always single-precision
/qemu/target/hexagon/
H A Darch.c2 * Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
70 {22, 27, 32, 37},
74 {18, 22, 26, 30},
77 {15, 19, 22, 25},
80 {13, 16, 19, 22},
103 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
114 16, 16, 18, 18, 19, 19, 21, 21, 22, 22,
176 } else if ((a & ((1 << (n - 1)) - 1)) == 0) { /* N-1..0 all zero? */ in conv_round()
180 val = ((fSE32_64(a)) + (1 << (n - 1))); in conv_round()
198 set_float_exception_flags(0, &env->fp_status); in arch_fpop_start()
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/qemu/include/hw/i2c/
H A Dpnv_i2c_regs.h4 * Copyright (c) 2024, IBM Corporation.
6 * SPDX-License-Identifier: GPL-2.0-or-later
68 #define I2C_INTR_DATA_REQ PPC_BIT(22)
96 #define I2C_STAT_PORT_BUSY PPC_BIT(22)
109 /* Pseudo-status used for timeouts */
122 #define I2C_EXTD_STAT_HIGH_WATER PPC_BIT(22)
/qemu/include/hw/misc/
H A Dimx25_ccm.h4 * Copyright (C) 2012 NICTA
5 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
8 * See the COPYING file in the top-level directory.
39 #define IMX25_CCM_PMCR0_REG 22
52 #define CCTL_MPLL_BYPASS_SHIFT (22)
H A Daspeed_scu.h9 * the COPYING file in the top-level directory.
19 #define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400"
20 #define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500"
21 #define TYPE_ASPEED_2600_SCU TYPE_ASPEED_SCU "-ast2600"
22 #define TYPE_ASPEED_2700_SCU TYPE_ASPEED_SCU "-ast2700"
23 #define TYPE_ASPEED_2700_SCUIO TYPE_ASPEED_SCU "io" "-ast2700"
24 #define TYPE_ASPEED_1030_SCU TYPE_ASPEED_SCU "-ast1030"
86 * arch/arm/mach-aspeed/include/mach/regs-scu.h
88 * Copyright (C) 2012-2020 ASPEED Technology Inc.
106 * 22:20 LPC Host LHCLK divider selection
[all …]
/qemu/scripts/kvm/
H A Dvmxcap5 # Copyright 2009-2010 Red Hat, Inc.
11 # the COPYING file in the top-level directory.
74 print(' %-40s %s' % (self.bits[bit], s))
76 # All 64 bits in the tertiary controls MSR are allowed-1
105 v = (value >> lo) & ((1 << (hi - lo + 1)) - 1)
106 print(' %-40s %s' % (self.bits[bits], fmt(v)))
115 49: 'Dual-monitor support',
125 name = 'pin-based controls',
130 6: 'Activate VMX-preemption timer',
138 name = 'primary processor-based controls',
[all …]
/qemu/target/rx/
H A Dgdbstub.c4 * Copyright (c) 2019 Yoshinori Sato
28 return gdb_get_regl(mem_buf, env->regs[n]); in rx_cpu_gdb_read_register()
30 return gdb_get_regl(mem_buf, (env->psw_u) ? env->regs[0] : env->usp); in rx_cpu_gdb_read_register()
32 return gdb_get_regl(mem_buf, (!env->psw_u) ? env->regs[0] : env->isp); in rx_cpu_gdb_read_register()
36 return gdb_get_regl(mem_buf, env->pc); in rx_cpu_gdb_read_register()
38 return gdb_get_regl(mem_buf, env->intb); in rx_cpu_gdb_read_register()
40 return gdb_get_regl(mem_buf, env->bpsw); in rx_cpu_gdb_read_register()
41 case 22: in rx_cpu_gdb_read_register()
42 return gdb_get_regl(mem_buf, env->bpc); in rx_cpu_gdb_read_register()
44 return gdb_get_regl(mem_buf, env->fintv); in rx_cpu_gdb_read_register()
[all …]
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc4 * Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH
10 * See the COPYING file in the top-level directory for details.
28 /* We're going to re-use TCGType in setting of the SF bit, which controls
67 /* V8 - V15 are call-saved, and skipped. */
96 ptrdiff_t offset = target - src_rx;
110 ptrdiff_t offset = target - src_rx;
122 ptrdiff_t offset = target - src_rx;
159 /* Match a constant valid for addition (12-bit, optionally shifted). */
182 val += val & -val;
183 return (val & (val - 1)) == 0;
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/qemu/gdb-xml/
H A Daarch64-core.xml2 <!-- Copyright (C) 2009-2025 Free Software Foundation, Inc.
7 notice and this notice are preserved. -->
9 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
47 <!-- Stack Pointer. -->
50 <!-- Exception Level. -->
52 <!-- Execution state. -->
55 <!-- FIQ interrupt mask. -->
57 <!-- IRQ interrupt mask. -->
59 <!-- SError interrupt mask. -->
61 <!-- Debug exception mask. -->
[all …]
/qemu/include/hw/arm/
H A Domap.h4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
24 #include "target/arm/cpu-qom.h"
47 /* omap_clk.c */
61 /* omap_intc.c */
62 #define TYPE_OMAP_INTC "omap-intc"
84 /* omap_i2c.c */
93 /* omap_gpio.c */
94 #define TYPE_OMAP1_GPIO "omap-gpio"
104 * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
119 #define OMAP_INT_DMA_CH3 22
[all …]
/qemu/target/sh4/
H A Dgdbstub.c4 * Copyright (c) 2003-2005 Fabrice Bellard
5 * Copyright (c) 2013 SUSE LINUX Products GmbH
33 if ((env->sr & (1u << SR_MD)) && (env->sr & (1u << SR_RB))) { in superh_cpu_gdb_read_register()
34 return gdb_get_regl(mem_buf, env->gregs[n + 16]); in superh_cpu_gdb_read_register()
36 return gdb_get_regl(mem_buf, env->gregs[n]); in superh_cpu_gdb_read_register()
39 return gdb_get_regl(mem_buf, env->gregs[n]); in superh_cpu_gdb_read_register()
41 return gdb_get_regl(mem_buf, env->pc); in superh_cpu_gdb_read_register()
43 return gdb_get_regl(mem_buf, env->pr); in superh_cpu_gdb_read_register()
45 return gdb_get_regl(mem_buf, env->gbr); in superh_cpu_gdb_read_register()
47 return gdb_get_regl(mem_buf, env->vbr); in superh_cpu_gdb_read_register()
[all …]
/qemu/tests/unit/
H A Dtest-string-output-visitor.c2 * String Output Visitor unit-tests.
4 * Copyright (C) 2012 Red Hat Inc.
7 * Paolo Bonzini <pbonzini@redhat.com> (based on test-qobject-output-visitor)
10 * See the COPYING file in the top-level directory.
16 #include "qapi/string-output-visitor.h"
17 #include "test-qapi-visit.h"
28 data->human = human; in visitor_output_setup_internal()
29 data->ov = string_output_visitor_new(human, &data->str); in visitor_output_setup_internal()
30 g_assert(data->ov); in visitor_output_setup_internal()
48 visit_free(data->ov); in visitor_output_teardown()
[all …]
/qemu/hw/intc/
H A Dxlnx-pmu-iomod-intc.c4 * Copyright (c) 2013 Xilinx Inc
34 #include "hw/intc/xlnx-pmu-iomod-intc.h"
36 #include "hw/qdev-properties.h"
87 FIELD(GPO3, PL_GPO_22, 22, 1)
120 FIELD(GPI0, RFT_MISMATCH_CPU, 22, 1)
145 FIELD(GPI1, ACPU_2_DBG_PWRUP, 22, 1)
170 FIELD(GPI2, DBG_ACPU2_RST_REQ, 22, 1)
195 FIELD(GPI3, PL_GPI_22, 22, 1)
227 FIELD(IRQ_STATUS, IPI3, 22, 1)
251 FIELD(IRQ_PENDING, IPI3, 22, 1)
[all …]
/qemu/ui/
H A Dcurses_keys.h4 * Copyright (c) 2005 Andrzej Zaborowski <balrog@zabor.org>
56 [0 ... (CURSES_CHARS - 1)] = -1,
65 [0 ... (CURSES_KEYS - 1)] = -1,
73 [0 ... (CURSES_CHARS - 1)] = -1,
86 ['-'] = 12,
97 ['u'] = 22,
122 ['c'] = 46,
152 ['U'] = 22 | SHIFT,
175 ['C'] = 46 | SHIFT,
184 ['Q' - '@'] = 16 | CNTRL, /* Control + q */
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/qemu/target/mips/
H A Dcpu.h4 #include "cpu-qom.h"
5 #include "exec/cpu-common.h"
6 #include "exec/cpu-defs.h"
7 #include "exec/cpu-interrupt.h"
11 #include "fpu/softfloat-types.h"
13 #include "mips-defs.h"
32 uint64_t d; /* binary double fixed-point */
33 uint32_t w[2]; /* binary single fixed-point */
34 /* FPU/MSA register mapping is not tested on big-endian hosts. */
57 #define FCR0_F64 22
[all …]
/qemu/target/tricore/
H A Dcpu.h4 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
23 #include "cpu-qom.h"
25 #include "exec/cpu-common.h"
26 #include "exec/cpu-defs.h"
27 #include "qemu/cpu-float.h"
28 #include "tricore-defs.h"
87 FIELD(PCXI, PCPN_161, 22, 8)
90 FIELD(PCXI, UL_13, 22, 1)
150 TRICORE_PRIV_UM0 = 0x0, /* user mode-0 flag */
151 TRICORE_PRIV_UM1 = 0x1, /* user mode-1 flag */
[all …]

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