4  * Copyright (c) 2013 Xilinx Inc
34 #include "hw/intc/xlnx-pmu-iomod-intc.h"
36 #include "hw/qdev-properties.h"
87     FIELD(GPO3, PL_GPO_22, 22, 1)
120     FIELD(GPI0, RFT_MISMATCH_CPU, 22, 1)
145     FIELD(GPI1, ACPU_2_DBG_PWRUP, 22, 1)
170     FIELD(GPI2, DBG_ACPU2_RST_REQ, 22, 1)
195     FIELD(GPI3, PL_GPI_22, 22, 1)
227     FIELD(IRQ_STATUS, IPI3, 22, 1)
251     FIELD(IRQ_PENDING, IPI3, 22, 1)
275     FIELD(IRQ_ENABLE, IPI3, 22, 1)
299     FIELD(IRQ_ACK, IPI3, 22, 1)
339     s->regs[R_IRQ_PENDING] = s->regs[R_IRQ_STATUS] & s->regs[R_IRQ_ENABLE];  in xlnx_pmu_io_irq_update()
340     irq_out = !!s->regs[R_IRQ_PENDING];  in xlnx_pmu_io_irq_update()
344     qemu_set_irq(s->parent_irq, irq_out);  in xlnx_pmu_io_irq_update()
349     XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(reg->opaque);  in xlnx_pmu_io_irq_enable_postw()
356     XlnxPMUIOIntc *s = XLNX_PMU_IO_INTC(reg->opaque);  in xlnx_pmu_io_irq_ack_postw()
360     val &= s->regs[R_IRQ_STATUS];  in xlnx_pmu_io_irq_ack_postw()
361     s->regs[R_IRQ_STATUS] ^= val;  in xlnx_pmu_io_irq_ack_postw()
364     s->regs[R_IRQ_STATUS] |= s->irq_raw & ~s->cfg.level_edge;  in xlnx_pmu_io_irq_ack_postw()
433     uint32_t prev = s->irq_raw;  in irq_handler()
436     s->irq_raw &= ~mask;  in irq_handler()
437     s->irq_raw |= (!!level) << irq;  in irq_handler()
439     /* Turn active-low into active-high.  */  in irq_handler()
440     s->irq_raw ^= (~s->cfg.positive);  in irq_handler()
441     s->irq_raw &= mask;  in irq_handler()
443     if (s->cfg.level_edge & mask) {  in irq_handler()
445         temp = (prev ^ s->irq_raw) & s->irq_raw;  in irq_handler()
448         temp = s->irq_raw;  in irq_handler()
450     s->regs[R_IRQ_STATUS] |= temp;  in irq_handler()
460     for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {  in xlnx_pmu_io_intc_reset()
461         register_reset(&s->regs_info[i]);  in xlnx_pmu_io_intc_reset()
478     DEFINE_PROP_UINT32("intc-intr-size", XlnxPMUIOIntc, cfg.intr_size, 0),
479     DEFINE_PROP_UINT32("intc-level-edge", XlnxPMUIOIntc, cfg.level_edge, 0),
480     DEFINE_PROP_UINT32("intc-positive", XlnxPMUIOIntc, cfg.positive, 0),
488     s->cfg.level_edge <<= 16;  in xlnx_pmu_io_intc_realize()
489     s->cfg.level_edge |= 0xffff;  in xlnx_pmu_io_intc_realize()
492     s->cfg.positive <<= 16;  in xlnx_pmu_io_intc_realize()
493     s->cfg.positive |= 0xffff;  in xlnx_pmu_io_intc_realize()
496     assert(s->cfg.intr_size <= 16);  in xlnx_pmu_io_intc_realize()
498     qdev_init_gpio_in(dev, irq_handler, 16 + s->cfg.intr_size);  in xlnx_pmu_io_intc_realize()
507     memory_region_init(&s->iomem, obj, TYPE_XLNX_PMU_IO_INTC,  in xlnx_pmu_io_intc_init()
512                               s->regs_info, s->regs,  in xlnx_pmu_io_intc_init()
516     memory_region_add_subregion(&s->iomem,  in xlnx_pmu_io_intc_init()
518                                 &reg_array->mem);  in xlnx_pmu_io_intc_init()
519     sysbus_init_mmio(sbd, &s->iomem);  in xlnx_pmu_io_intc_init()
521     sysbus_init_irq(sbd, &s->parent_irq);  in xlnx_pmu_io_intc_init()
539     dc->realize = xlnx_pmu_io_intc_realize;  in xlnx_pmu_io_intc_class_init()
540     dc->vmsd = &vmstate_xlnx_pmu_io_intc;  in xlnx_pmu_io_intc_class_init()