178e138bcSPeter Maydell# AArch32 VFP instruction descriptions (unconditional insns) 278e138bcSPeter Maydell# 378e138bcSPeter Maydell# Copyright (c) 2019 Linaro, Ltd 478e138bcSPeter Maydell# 578e138bcSPeter Maydell# This library is free software; you can redistribute it and/or 678e138bcSPeter Maydell# modify it under the terms of the GNU Lesser General Public 778e138bcSPeter Maydell# License as published by the Free Software Foundation; either 8*50f57e09SChetan Pant# version 2.1 of the License, or (at your option) any later version. 978e138bcSPeter Maydell# 1078e138bcSPeter Maydell# This library is distributed in the hope that it will be useful, 1178e138bcSPeter Maydell# but WITHOUT ANY WARRANTY; without even the implied warranty of 1278e138bcSPeter Maydell# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 1378e138bcSPeter Maydell# Lesser General Public License for more details. 1478e138bcSPeter Maydell# 1578e138bcSPeter Maydell# You should have received a copy of the GNU Lesser General Public 1678e138bcSPeter Maydell# License along with this library; if not, see <http://www.gnu.org/licenses/>. 1778e138bcSPeter Maydell 1878e138bcSPeter Maydell# 1978e138bcSPeter Maydell# This file is processed by scripts/decodetree.py 2078e138bcSPeter Maydell# 2178e138bcSPeter Maydell# Encodings for the unconditional VFP instructions are here: 2278e138bcSPeter Maydell# generally anything matching A32 2378e138bcSPeter Maydell# 1111 1110 .... .... .... 101. ...0 .... 2478e138bcSPeter Maydell# and T32 2578e138bcSPeter Maydell# 1111 110. .... .... .... 101. .... .... 2678e138bcSPeter Maydell# 1111 1110 .... .... .... 101. .... .... 2778e138bcSPeter Maydell# (but those patterns might also cover some Neon instructions, 2878e138bcSPeter Maydell# which do not live in this file.) 29b3ff4b87SPeter Maydell 30b3ff4b87SPeter Maydell# VFP registers have an odd encoding with a four-bit field 31b3ff4b87SPeter Maydell# and a one-bit field which are assembled in different orders 32b3ff4b87SPeter Maydell# depending on whether the register is double or single precision. 33b3ff4b87SPeter Maydell# Each individual instruction function must do the checks for 34b3ff4b87SPeter Maydell# "double register selected but CPU does not have double support" 35b3ff4b87SPeter Maydell# and "double register number has bit 4 set but CPU does not 36b3ff4b87SPeter Maydell# support D16-D31" (which should UNDEF). 37b3ff4b87SPeter Maydell%vm_dp 5:1 0:4 38b3ff4b87SPeter Maydell%vm_sp 0:4 5:1 39b3ff4b87SPeter Maydell%vn_dp 7:1 16:4 40b3ff4b87SPeter Maydell%vn_sp 16:4 7:1 41b3ff4b87SPeter Maydell%vd_dp 22:1 12:4 42b3ff4b87SPeter Maydell%vd_sp 12:4 22:1 43b3ff4b87SPeter Maydell 44f2eafb75SRichard Henderson@vfp_dnm_s ................................ vm=%vm_sp vn=%vn_sp vd=%vd_sp 45f2eafb75SRichard Henderson@vfp_dnm_d ................................ vm=%vm_dp vn=%vn_dp vd=%vd_dp 46f2eafb75SRichard Henderson 4711e78fecSPeter MaydellVSEL 1111 1110 0. cc:2 .... .... 1001 .0.0 .... \ 4811e78fecSPeter Maydell vm=%vm_sp vn=%vn_sp vd=%vd_sp sz=1 49b3ff4b87SPeter MaydellVSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \ 5011e78fecSPeter Maydell vm=%vm_sp vn=%vn_sp vd=%vd_sp sz=2 51b3ff4b87SPeter MaydellVSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \ 5211e78fecSPeter Maydell vm=%vm_dp vn=%vn_dp vd=%vd_dp sz=3 53f65988a1SPeter Maydell 54120a0eb3SPeter MaydellVMAXNM_hp 1111 1110 1.00 .... .... 1001 .0.0 .... @vfp_dnm_s 55120a0eb3SPeter MaydellVMINNM_hp 1111 1110 1.00 .... .... 1001 .1.0 .... @vfp_dnm_s 56120a0eb3SPeter Maydell 57f2eafb75SRichard HendersonVMAXNM_sp 1111 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s 58f2eafb75SRichard HendersonVMINNM_sp 1111 1110 1.00 .... .... 1010 .1.0 .... @vfp_dnm_s 59f2eafb75SRichard Henderson 60f2eafb75SRichard HendersonVMAXNM_dp 1111 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d 61f2eafb75SRichard HendersonVMINNM_dp 1111 1110 1.00 .... .... 1011 .1.0 .... @vfp_dnm_d 62e3bb599dSPeter Maydell 630a6f4b4cSPeter MaydellVRINT 1111 1110 1.11 10 rm:2 .... 1001 01.0 .... \ 640a6f4b4cSPeter Maydell vm=%vm_sp vd=%vd_sp sz=1 65e3bb599dSPeter MaydellVRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \ 660a6f4b4cSPeter Maydell vm=%vm_sp vd=%vd_sp sz=2 67e3bb599dSPeter MaydellVRINT 1111 1110 1.11 10 rm:2 .... 1011 01.0 .... \ 680a6f4b4cSPeter Maydell vm=%vm_dp vd=%vd_dp sz=3 69c2a46a91SPeter Maydell 70c2a46a91SPeter Maydell# VCVT float to int with specified rounding mode; Vd is always single-precision 71c505bc6aSPeter MaydellVCVT 1111 1110 1.11 11 rm:2 .... 1001 op:1 1.0 .... \ 72c505bc6aSPeter Maydell vm=%vm_sp vd=%vd_sp sz=1 73c2a46a91SPeter MaydellVCVT 1111 1110 1.11 11 rm:2 .... 1010 op:1 1.0 .... \ 74c505bc6aSPeter Maydell vm=%vm_sp vd=%vd_sp sz=2 75c2a46a91SPeter MaydellVCVT 1111 1110 1.11 11 rm:2 .... 1011 op:1 1.0 .... \ 76c505bc6aSPeter Maydell vm=%vm_dp vd=%vd_sp sz=3 77e4875e3bSPeter Maydell 78f61e5c43SPeter MaydellVMOVX 1111 1110 1.11 0000 .... 1010 01 . 0 .... \ 79f61e5c43SPeter Maydell vd=%vd_sp vm=%vm_sp 80f61e5c43SPeter Maydell 81e4875e3bSPeter MaydellVINS 1111 1110 1.11 0000 .... 1010 11 . 0 .... \ 82e4875e3bSPeter Maydell vd=%vd_sp vm=%vm_sp 83