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/linux-3.3/include/linux/mfd/wm831x/
Dotp.h64 * R30726 (0x7806) - Unique ID 7
111 #define WM831X_OSC_TRIM_MASK 0x0780 /* OSC_TRIM - [10:7] */
112 #define WM831X_OSC_TRIM_SHIFT 7 /* OSC_TRIM - [10:7] */
113 #define WM831X_OSC_TRIM_WIDTH 4 /* OSC_TRIM - [10:7] */
124 #define WM831X_CHILD_I2C_ADDR_MASK 0x00FE /* CHILD_I2C_ADDR - [7:1] */
125 #define WM831X_CHILD_I2C_ADDR_SHIFT 1 /* CHILD_I2C_ADDR - [7:1] */
126 #define WM831X_CHILD_I2C_ADDR_WIDTH 7 /* CHILD_I2C_ADDR - [7:1] */
/linux-3.3/arch/xtensa/variants/s6000/include/variant/
Dhardware.h68 #define S6_GREG1_PLLSEL_AIM_PLLAIMREF 7
69 #define S6_GREG1_PLLSEL_AIM_MASK 7
78 #define S6_GREG1_PLLSEL_DDR_PLLIOREF 7
79 #define S6_GREG1_PLLSEL_DDR_MASK 7
130 #define S6_GREG1_BLOCK_SB 7
171 #define S6_GREG1_BOOT_CFG0_DOWNSTREAM 7
179 #define S6_GREG1_BOOT_CFG0_PLLSYSDIV_MASK 7
197 #define S6_GREG1_DRAMBUSYHOLDOF_XT_MASK 7
215 #define S6_INTC_DMA_LMSERR 7
/linux-3.3/arch/arm/mach-omap2/
Dgpmc-onenand.c40 const int t_aavdh = 7; in omap2_onenand_set_async_mode()
232 t_ces = 7; in omap2_onenand_set_sync_mode()
233 t_avds = 7; in omap2_onenand_set_sync_mode()
234 t_avdh = 7; in omap2_onenand_set_sync_mode()
236 t_aavdh = 7; in omap2_onenand_set_sync_mode()
269 t_ces = 7; in omap2_onenand_set_sync_mode()
270 t_avds = 7; in omap2_onenand_set_sync_mode()
280 reg |= (1 << 7); in omap2_onenand_set_sync_mode()
283 reg |= (1 << 7); in omap2_onenand_set_sync_mode()
286 reg |= (1 << 7); in omap2_onenand_set_sync_mode()
[all …]
/linux-3.3/arch/cris/include/arch-v32/mach-a3/mach/hwregs/asm/
Dpinmux_defs_asm.h75 #define reg_pinmux_rw_hwprot___ser1___lsb 7
77 #define reg_pinmux_rw_hwprot___ser1___bit 7
150 #define reg_pinmux_rw_gio_pa___pa7___lsb 7
152 #define reg_pinmux_rw_gio_pa___pa7___bit 7
249 #define reg_pinmux_rw_gio_pb___pb7___lsb 7
251 #define reg_pinmux_rw_gio_pb___pb7___bit 7
348 #define reg_pinmux_rw_gio_pc___pc7___lsb 7
350 #define reg_pinmux_rw_gio_pc___pc7___bit 7
399 #define reg_pinmux_rw_iop_pa___pa7___lsb 7
401 #define reg_pinmux_rw_iop_pa___pa7___bit 7
[all …]
/linux-3.3/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h284 #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
285 #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
286 #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
287 #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
288 #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
289 #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
290 #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
291 #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
292 #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
293 #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
[all …]
/linux-3.3/scripts/dtc/
Ddtc-lexer.lex.c_shipped379 7, 0, 0, 0, 0, 0, 0, 0, 5, 0,
380 9, 9, 11, 11, 6, 0, 7, 0, 0, 0,
395 1, 7, 5, 5, 8, 5, 9, 10, 11, 12,
424 4, 4, 5, 6, 7, 7, 1, 1, 6, 6,
425 6, 6, 7, 7, 7, 7, 7, 7, 7, 7,
426 7, 8, 1
447 93, 1, 1, 1, 1, 5, 93, 7, 1, 1,
501 9, 9, 5, 5, 5, 5, 5, 7, 7, 7,
502 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
503 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
[all …]
/linux-3.3/sound/soc/codecs/
D88pm860x-codec.c36 #define MIC_STATUS (1 << 7)
67 #define PCM_MODE_MASK 7
73 #define DAC_MUTE (1 << 7)
109 #define CLR_SHORT_LO2 (1 << 7)
165 4, 7, TLV_DB_SCALE_ITEM(-900, 300, 0),
172 3, 7, TLV_DB_SCALE_ITEM(-600, 600, 0),
175 /* {-16, -13, -10, -7, -5.2, -3,3, -2.2, 0}dB, mute instead of -16dB */
181 6, 7, TLV_DB_SCALE_ITEM(-220, 220, 0),
189 6, 7, TLV_DB_SCALE_ITEM(-10351, 116, 0),
205 {-10643, 5, 15}, {-10485, 3, 14}, {-10351, 7, 15}, {-10235, 1, 12},
[all …]
Dda7210.c87 #define DA7210_MIC_L_EN (1 << 7)
90 #define DA7210_MIC_R_EN (1 << 7)
93 #define DA7210_IN_L_EN (1 << 7)
96 #define DA7210_IN_R_EN (1 << 7)
101 #define DA7210_ADC_R_EN (1 << 7)
106 #define DA7210_VOICE_EN (1 << 7)
112 #define DA7210_DAC_R_EN (1 << 7)
115 #define DA7210_OUT_L_EN (1 << 7)
118 #define DA7210_OUT_R_EN (1 << 7)
125 #define DA7210_HP_R_EN (1 << 7)
[all …]
Dwm8995.h775 #define WM8995_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */
843 #define WM8995_DMIC3L_ENA_SHIFT 7 /* DMIC3L_ENA */
924 #define WM8995_DMIC_SRC1_MASK 0x00C0 /* DMIC_SRC1 - [7:6] */
925 #define WM8995_DMIC_SRC1_SHIFT 6 /* DMIC_SRC1 - [7:6] */
926 #define WM8995_DMIC_SRC1_WIDTH 2 /* DMIC_SRC1 - [7:6] */
952 #define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */
967 #define WM8995_IN1_VU_SHIFT 7 /* IN1_VU */
1001 #define WM8995_DAC1L_VOL_MASK 0x00FF /* DAC1L_VOL - [7:0] */
1002 #define WM8995_DAC1L_VOL_SHIFT 0 /* DAC1L_VOL - [7:0] */
1003 #define WM8995_DAC1L_VOL_WIDTH 8 /* DAC1L_VOL - [7:0] */
[all …]
Dwm8996.h767 #define WM8996_HPOUT2L_ENA_SHIFT 7 /* HPOUT2L_ENA */
959 * R7 (0x07) - Power Management (7)
971 #define WM8996_ADC_DMIC_DSP2R_ENA_SHIFT 7 /* ADC_DMIC_DSP2R_ENA */
995 #define WM8996_AIF2TX_SRC_MASK 0x00C0 /* AIF2TX_SRC - [7:6] */
996 #define WM8996_AIF2TX_SRC_SHIFT 6 /* AIF2TX_SRC - [7:6] */
997 #define WM8996_AIF2TX_SRC_WIDTH 2 /* AIF2TX_SRC - [7:6] */
1012 #define WM8996_IN1_VU_SHIFT 7 /* IN1_VU */
1027 #define WM8996_IN1_VU_SHIFT 7 /* IN1_VU */
1050 #define WM8996_DAC1R_HPOUT1R_VOL_MASK 0x00F0 /* DAC1R_HPOUT1R_VOL - [7:4] */
1051 #define WM8996_DAC1R_HPOUT1R_VOL_SHIFT 4 /* DAC1R_HPOUT1R_VOL - [7:4] */
[all …]
Dwm8991.h128 #define WM8991_LIN34_ENA_BIT 7
152 #define WM8991_LOPGA_ENA_BIT 7
233 #define WM8991_ADC_CLKDIV_MASK 0x00E0 /* ADC_CLKDIV - [7:5] */
285 #define WM8991_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */
291 #define WM8991_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */
321 #define WM8991_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */
328 #define WM8991_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */
428 #define WM8991_LI12MUTE_BIT 7
438 #define WM8991_LI34MUTE_BIT 7
449 #define WM8991_RI12MUTE_BIT 7
[all …]
Dwm8990.h130 #define WM8990_LIN34_ENA_BIT 7
154 #define WM8990_LOPGA_ENA_BIT 7
287 #define WM8990_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */
293 #define WM8990_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */
323 #define WM8990_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */
330 #define WM8990_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */
430 #define WM8990_LI12MUTE_BIT 7
440 #define WM8990_LI34MUTE_BIT 7
451 #define WM8990_RI12MUTE_BIT 7
462 #define WM8990_RI34MUTE_BIT 7
[all …]
Dwm8750.c85 SOC_ENUM_SINGLE(WM8750_BASS, 7, 2, wm8750_bass),
90 SOC_ENUM_SINGLE(WM8750_3D, 7, 2, wm8750_3d_func),
91 SOC_ENUM_SINGLE(WM8750_ALC1, 7, 4, wm8750_alc_func),
97 SOC_ENUM_SINGLE(WM8750_ADCTL2, 7, 4, wm8750_out3),
109 SOC_DOUBLE_R("Capture Switch", WM8750_LINVOL, WM8750_RINVOL, 7, 1, 1),
112 WM8750_ROUT1V, 7, 1, 0),
114 WM8750_ROUT2V, 7, 1, 0),
119 SOC_SINGLE("Playback 6dB Attenuate", WM8750_ADCDAC, 7, 1, 0),
137 SOC_SINGLE("ALC Capture Target Volume", WM8750_ALC1, 0, 7, 0),
138 SOC_SINGLE("ALC Capture Max Volume", WM8750_ALC1, 4, 7, 0),
[all …]
/linux-3.3/arch/mips/include/asm/octeon/
Dcvmx-dpi-defs.h33 #define CVMX_DPI_DMAX_COUNTS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000300ull) + ((offset) & 7) * 8)
34 #define CVMX_DPI_DMAX_DBELL(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000200ull) + ((offset) & 7) * 8)
35 … CVMX_DPI_DMAX_ERR_RSP_STATUS(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A80ull) + ((offset) & 7) * 8)
36 #define CVMX_DPI_DMAX_IBUFF_SADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000280ull) + ((offset) & 7) …
37 #define CVMX_DPI_DMAX_IFLIGHT(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000A00ull) + ((offset) & 7) * 8)
38 #define CVMX_DPI_DMAX_NADDR(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000380ull) + ((offset) & 7) * 8)
39 #define CVMX_DPI_DMAX_REQBNK0(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000400ull) + ((offset) & 7) * 8)
40 #define CVMX_DPI_DMAX_REQBNK1(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000480ull) + ((offset) & 7) * 8)
42 #define CVMX_DPI_DMA_ENGX_EN(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000080ull) + ((offset) & 7) * 8)
44 #define CVMX_DPI_ENGX_BUF(offset) (CVMX_ADD_IO_SEG(0x0001DF0000000880ull) + ((offset) & 7) * 8)
[all …]
/linux-3.3/drivers/media/video/s5p-tv/
Dregs-mixer.h62 #define MXR_STATUS_16_BURST (1 << 7)
63 #define MXR_STATUS_BURST_MASK (1 << 7)
71 #define MXR_CFG_DST_SDO (0 << 7)
72 #define MXR_CFG_DST_HDMI (1 << 7)
73 #define MXR_CFG_DST_MASK (1 << 7)
92 #define MXR_GRP_CFG_ALPHA_VAL(x) MXR_MASK_VAL(x, 7, 0)
118 #define MXR_LAYER_CFG_GRP0_VAL(x) MXR_MASK_VAL(x, 7, 4)
/linux-3.3/arch/blackfin/mach-bf527/include/mach/
DdefBF522.h90 /* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
126 #define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
127 #define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
128 #define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
129 #define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
319 #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
320 #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
321 #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
322 #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
323 #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
[all …]
/linux-3.3/arch/cris/include/arch-v32/arch/hwregs/iop/asm/
Diop_sw_mpu_defs_asm.h72 #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7
74 #define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7
113 #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7
115 #define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7
273 #define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7
275 #define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7
372 #define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7
374 #define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7
471 #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7
473 #define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7
[all …]
/linux-3.3/drivers/net/ethernet/marvell/
Dskge.h14 #define PCI_VPD_ROM_SZ 7L<<14 /* VPD ROM size 0=256, 1=512, ... */
144 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
154 /* Bit 7.. 2: reserved */
159 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
201 IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */
228 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
245 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
257 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
274 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
309 GP_IO_7 = 1<<7, /* IO_7 pin */
[all …]
/linux-3.3/drivers/net/ethernet/i825xx/
Dether1.h85 #define RFD_FRAMESHORT (1 << 7)
143 #define CFG8_SAVEBADF (1 << 7)
152 #define CFG9_ELOOPBACK (1 << 7)
156 #define CFG10_BOFMET (1 << 7)
170 #define CFG14_FLGPAD (1 << 7)
175 #define CFG15_ICDS (1 << 7)
181 #define SCB_STRXMASK (7 << 4) /* Receive unit status */
186 #define SCB_STCUMASK (7 << 8) /* Command unit status */
240 #define CMD_DIAGNOSE 7
242 #define CMD_MASK 7
[all …]
/linux-3.3/drivers/s390/net/
Dctcm_fsms.h288 No XID2(7)'s have yet been received.
289 XID2(7) negotiations pending.
291 MPCG_STATE_XID7INITX XID2(7) negotiations in progress.
292 At least 1, but not all, XID2(7)'s
295 MPCG_STATE_XID7INITF XID2(7) negotiations complete.
314 No XID2(7)'s have yet been received.
315 XID2(7) negotiations pending.
317 MPCG_STATE_XID7INITZ XID2(7) negotiations in progress.
318 At least 1, but not all, XID2(7)'s
321 MPCG_STATE_XID7INITF XID2(7) negotiations complete.
/linux-3.3/arch/arm/kernel/
Dkprobes-test-thumb.c67 TEST_R( "lsls r0, r",7,VAL2,", #11") in kprobe_thumb16_test_cases()
69 TEST_R( "lsrs r0, r",7,VAL2,", #11") in kprobe_thumb16_test_cases()
71 TEST_R( "asrs r0, r",7,VAL2,", #11") in kprobe_thumb16_test_cases()
72 TEST_RR( "adds r2, r",0,VAL1,", r",7,VAL2,"") in kprobe_thumb16_test_cases()
73 TEST_RR( "adds r5, r",7,VAL2,", r",0,VAL2,"") in kprobe_thumb16_test_cases()
74 TEST_RR( "subs r2, r",0,VAL1,", r",7,VAL2,"") in kprobe_thumb16_test_cases()
75 TEST_RR( "subs r5, r",7,VAL2,", r",0,VAL2,"") in kprobe_thumb16_test_cases()
77 TEST_R( "adds r0, r",7,VAL2,", #2") in kprobe_thumb16_test_cases()
79 TEST_R( "subs r0, r",7,VAL2,", #2") in kprobe_thumb16_test_cases()
84 TEST_R( "cmp.n r",7,0xa0, ", #0xa0") in kprobe_thumb16_test_cases()
[all …]
/linux-3.3/drivers/ata/
Dpata_ns87410.c74 6, 7, 7, 7, 7 in ns87410_set_piomode()
78 0, 1, 2, 3, 4, 5, 6, 6, 7, 7, 7, 7 in ns87410_set_piomode()
/linux-3.3/sound/pci/ca0106/
Dca0106.h15 * 0.0.7
152 /* Here pins 0,1,2,3,4,,6 are output. 5,7 are input */
313 * SPDIF 0 User data [7:0]
334 …/* Record Map [7:0] (2 bits per channel) 0=mapped to channel 0, 1=mapped to channel 1, 2=mapped to…
347 #define CAPTURE_VOLUME2 0x62 /* Capture volume per channel 4-7 */
349 #define PLAYBACK_ROUTING1 0x63 /* Playback routing of channels 0-7. Effects AC3 ou…
356 /* Host channel 0 [2:0] -> SPDIF Mixer/Router channel 0-7.
357 * Host channel 1 [6:4] -> SPDIF Mixer/Router channel 0-7.
358 * Host channel 2 [10:8] -> SPDIF Mixer/Router channel 0-7.
359 * Host channel 3 [14:12] -> SPDIF Mixer/Router channel 0-7.
[all …]
/linux-3.3/drivers/net/wireless/zd1211rw/
Dzd_rf_uw2453.c61 RF_CHANNEL( 7) = 0x57,
81 RF_CHANNEL( 7) = 0x998,
98 static const u16 uw2453_std_vco_cfg[][7] = {
103 RF_CHANPAIR( 7, 8) = 0x6475,
112 RF_CHANPAIR( 7, 8) = 0x644d,
121 RF_CHANPAIR( 7, 8) = 0x646d,
130 RF_CHANPAIR( 7, 8) = 0x645d,
139 RF_CHANPAIR( 7, 8) = 0x647d,
148 RF_CHANPAIR( 7, 8) = 0x6443,
153 { /* table 7 */
[all …]
/linux-3.3/arch/x86/kvm/
Di8259.c130 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) in get_priority()
159 return (priority + s->priority_add) & 7; in pic_get_irq()
198 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); in kvm_pic_set_irq()
200 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr, in kvm_pic_set_irq()
222 s->priority_add = (irq + 1) & 7; in pic_intack()
245 irq2 = 7; in kvm_pic_read_irq()
254 irq = 7; in kvm_pic_read_irq()
342 irq = (priority + s->priority_add) & 7; in pic_ioport_write()
344 s->priority_add = (irq + 1) & 7; in pic_ioport_write()
350 irq = val & 7; in pic_ioport_write()
[all …]

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