Lines Matching full:7
284 #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
285 #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
286 #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
287 #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
288 #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
289 #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
290 #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
291 #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
292 #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
293 #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
294 #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
295 #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
296 #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
386 #define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */
387 #define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
388 #define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
389 #define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */
390 #define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
391 #define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
392 #define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
393 #define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
397 #define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */
398 #define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
399 #define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
400 #define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */
401 #define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
402 #define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
403 #define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
404 #define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
407 #define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */
408 #define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
409 #define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
410 #define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */
411 #define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
412 #define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
413 #define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
414 #define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
599 #define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */
614 #define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */
643 #define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */
658 #define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */
689 #define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */
704 #define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */
733 #define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */
748 #define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */
775 #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
790 #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
797 #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */