Home
last modified time | relevance | path

Searched +full:4 +full:- +full:cores (Results 1 – 25 of 96) sorted by relevance

1234

/qemu/tests/unit/
H A Dtest-smp-parse.c2 * SMP parsing unit-tests
10 * See the COPYING.LIB file in the top-level directory.
26 #define SMP_MACHINE_NAME "TEST-SMP"
29 * Used to define the generic 3-level CPU topology hierarchy
30 * -sockets/cores/threads
36 .has_cores = hc, .cores = c, \
45 .cores = c, \
51 * Currently a 5-level topology hierarchy is supported on PC machines
52 * -sockets/dies/modules/cores/threads
61 .has_cores = he, .cores = e, \
[all …]
/qemu/docs/system/arm/
H A Draspi.rst8 ARM1176JZF-S core, 512 MiB of RAM
10 Cortex-A7 (4 cores), 1 GiB of RAM
12 Cortex-A53 (4 cores), 512 MiB of RAM
14 Cortex-A53 (4 cores), 1 GiB of RAM
16 Cortex-A72 (4 cores), 2 GiB of RAM
19 -------------------
21 * ARM1176JZF-S, Cortex-A7, Cortex-A53 or Cortex-A72 CPU
27 * Serial ports (BCM2835 AUX - 16550 based - and PL011)
41 ---------------
H A Dnuvoton.rst1 Nuvoton iBMC boards (``kudo-bmc``, ``mori-bmc``, ``npcm750-evb``, ``quanta-gbs-bmc``, ``quanta-gsj`…
4 The `Nuvoton iBMC`_ chips are a family of Arm-based SoCs that are
7 NPCM8XX series. NPCM7XX series feature one or two Arm Cortex-A9 CPU cores,
8 while NPCM8XX feature 4 Arm Cortex-A35 CPU cores. Both series contain a
12 .. _Nuvoton iBMC: https://www.nuvoton.com/products/cloud-computing/ibmc/
14 The NPCM750 SoC has two Cortex-A9 cores and is targeted for the Enterprise
17 - ``npcm750-evb`` Nuvoton NPCM750 Evaluation board
19 The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and
22 - ``quanta-gbs-bmc`` Quanta GBS server BMC
23 - ``quanta-gsj`` Quanta GSJ server BMC
[all …]
H A Dimx8mp-evk.rst1 NXP i.MX 8M Plus Evaluation Kit (``imx8mp-evk``)
4 The ``imx8mp-evk`` machine models the i.MX 8M Plus Evaluation Kit, based on an
8 -----------------
10 The ``imx8mp-evk`` machine implements the following devices:
12 * Up to 4 Cortex-A53 cores
14 * 4 UARTs
24 * Secure Non-Volatile Storage (SNVS) including an RTC
28 ------------
30 The ``imx8mp-evk`` machine can start a Linux kernel directly using the standard
31 ``-kernel`` functionality.
[all …]
H A Dsabrelite.rst4 Boundary Devices SABRE Lite i.MX6 Development Board is a low-cost development
9 -----------------
13 * Up to 4 Cortex-A9 cores
24 * 4 SDHC storage controllers
25 * 4 USB 2.0 host controllers
34 ------------
36 The SABRE Lite machine can start using the standard -kernel functionality
37 for loading a Linux kernel, U-Boot bootloader or ELF executable.
40 --------------------
46 .. code-block:: bash
[all …]
H A Dxlnx-versal-virt.rst1 Xilinx Versal Virt (``xlnx-versal-virt``)
4 Xilinx Versal is a family of heterogeneous multi-core SoCs
10 https://www.xilinx.com/products/silicon-devices/acap/versal.html
18 limitations. Currently, we support the following cores and devices:
20 Implemented CPU cores:
22 - 2 ACPUs (ARM Cortex-A72)
26 - Interrupt controller (ARM GICv3)
27 - 2 UARTs (ARM PL011)
28 - An RTC (Versal built-in)
29 - 2 GEMs (Cadence MACB Ethernet MACs)
[all …]
/qemu/docs/system/s390x/
H A Dcpu-topology.rst1 .. _cpu-topology-s390x:
8 tree-shaped hierarchy.
13 - CPU type
14 - entitlement
15 - dedication
17 Each bit set in the bitmap correspond to a core-id of a vCPU with matching
23 monitor polarization changes, see ``docs/devel/s390-cpu-topology.rst``.
26 -------------
31 The s390x host needs to use a Linux kernel v6.0 or newer (which provides the so-called
33 CPU topology facility via the so-called STFLE bit 11 to the VM).
[all …]
/qemu/docs/specs/
H A Drapl-msr.rst12 Thanks to KVM's `MSR filtering <msr-filter-patch_>`__ functionality,
17 .. _msr-filter-patch: https://patchwork.kernel.org/project/kvm/patch/20200916202951.23760-7-graf@am…
37 it with the UNIT provided above you'll get the power in micro-joules. This
45 core that belongs to PKG-0 will not be able to get the value of PKG-1 and
46 vice-versa.
49 -------------------------
60 3. Sleep for 1 second - During this pause the vcpu and other non-vcpu threads
63 4. Repeat 2. and 3. and calculate the delta of every metrics representing the
67 5. Filter the vcpu threads and the non-vcpu threads.
72 7. The total energy spent by the non-vcpu threads is divided by the number
[all …]
/qemu/docs/system/ppc/
H A Dpowernv.rst4 PowerNV (as Non-Virtualized) is the "bare metal" platform using the
16 -----------------
24 * Simple OCC is an on-chip micro-controller used for power management tasks.
30 ---------------
44 --------
49 GitHub <https://github.com/open-power>`_.
52 `OpenPOWER <https://github.com/open-power/op-build/releases/>`__ site.
58 ---------------------------
60 KVM acceleration in Linux Power hosts is provided by the kvm-hv and
61 kvm-pr modules. kvm-hv is adherent to PAPR and it's not compliant with
[all …]
/qemu/hw/ppc/
H A Dpnv.c4 * Copyright (c) 2016-2024, IBM Corporation.
6 * SPDX-License-Identifier: GPL-2.0-or-later
45 #include "target/ppc/mmu-hash64.h"
47 #include "hw/pci-host/pnv_phb.h"
48 #include "hw/pci-host/pnv_phb3.h"
49 #include "hw/pci-host/pnv_phb4.h"
52 #include "hw/qdev-properties.h"
58 #include "hw/char/serial-isa.h"
69 #define PNOR_FILE_NAME "pnv-pnor.bin"
79 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); in pnv_chip_core_typename()
[all …]
/qemu/include/hw/ppc/
H A Dpnv_chip.h4 #include "hw/pci-host/pnv_phb4.h"
36 PnvCore **cores; member
48 #define TYPE_PNV8_CHIP "pnv8-chip"
64 #define PNV8_CHIP_PHB3_MAX 4
75 #define TYPE_PNV9_CHIP "pnv9-chip"
99 #define PNV9_CHIP_MAX_I2C 4
104 * A SMT8 fused core is a pair of SMT4 cores.
109 #define TYPE_PNV10_CHIP "pnv10-chip"
136 #define PNV10_CHIP_MAX_I2C 4
/qemu/tests/functional/
H A Dtest_s390x_topology.py11 # later. See the COPYING file in the top-level directory.
21 S390x CPU topology consists of 4 topology layers, from bottom to top,
22 the cores, sockets, books and drawers and 2 modifiers attributes,
24 See: docs/system/s390x/cpu-topology.rst.
27 - implicitly from the '-smp' argument by completing each topology
30 - explicitly from the '-device' argument on the QEMU command line
31 - explicitly by hotplug of a new CPU using QMP or HMP
32 - it is modified by using QMP 'set-cpu-topology'
47 '/fedora-secondary/releases/35/Server/s390x/os'
53 '/fedora-secondary/releases/35/Server/s390x/os'
[all …]
H A Dtest_ppc64_pseries.py8 # later. See the COPYING file in the top-level directory.
17 panic_message = 'Kernel panic - not syncing'
21 ('https://archives.fedoraproject.org/pub/archive/fedora-secondary/'
29 self.vm.add_args('-kernel', kernel_path,
30 '-append', kernel_command_line)
35 self.vm.add_args('-machine', 'x-vof=on')
48 self.vm.add_args('-smp', '4')
50 console_pattern = 'smp: Brought up 1 node, 4 CPUs'
56 self.vm.add_args('-smp', '4')
59 console_pattern = 'smp: Brought up 1 node, 4 CPUs'
[all …]
H A Dtest_ppc64_powernv.py8 # later. See the COPYING file in the top-level directory.
17 panic_message = 'Kernel panic - not syncing'
21 ('https://archives.fedoraproject.org/pub/archive/fedora-secondary/'
30 self.vm.add_args('-kernel', kernel_path,
31 '-append', command_line)
42 self.vm.add_args('-smp', '4')
44 console_pattern = 'smp: Brought up 1 node, 4 CPUs'
50 self.vm.add_args('-smp', '4')
53 console_pattern = 'smp: Brought up 1 node, 4 CPUs'
54 wait_for_console_pattern(self, 'hash-mmu: Initializing hash mmu',
[all …]
/qemu/docs/system/riscv/
H A Dsifive_u.rst4 SiFive HiFive Unleashed Development Board is the ultimate RISC-V development
5 board featuring the Freedom U540 multi-core RISC-V processor.
8 -----------------
13 * Up to 4 U54 / U34 cores
15 * Platform-Level Interrupt Controller (PLIC)
17 * L2 Loosely Integrated Memory (L2-LIM)
22 * 1 One-Time Programmable (OTP) memory with stored serial number
30 1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode.
31 With QEMU, one can create a machine with 1 E51 core and up to 4 U54 cores. It
32 is also possible to create a 32-bit variant with the same peripherals except
[all …]
H A Dmicrochip-icicle-kit.rst1 Microchip PolarFire SoC Icicle Kit (``microchip-icicle-kit``)
5 SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA.
8 https://www.microchip.com/en-us/products/fpgas-and-plds/system-on-chip-fpgas/polarfire-soc-fpgas
11 https://www.microchip.com/en-us/development-tool/mpfs-icicle-kit-es
14 -----------------
16 The ``microchip-icicle-kit`` machine supports the following devices:
19 * 4 U54 cores
21 * Platform-Level Interrupt Controller (PLIC)
22 * L2 Loosely Integrated Memory (L2-LIM)
34 ------------
[all …]
/qemu/include/hw/intc/
H A Darm_gic.h23 * + QOM property "num-cpu": number of CPUs to support
24 * + QOM property "num-irq": number of IRQs (including both SPIs and PPIs)
26 * + QOM property "has-security-extensions": set true if the GIC should
28 * + QOM property "has-virtualization-extensions": set true if the GIC should
30 * + QOM property "first-cpu-index": index of the first cpu attached to the
32 * first-cpu-index, first-cpu-index + 1, ... first-cpu-index + num-cpu - 1.
33 * + unnamed GPIO inputs: (where P is number of SPIs, i.e. num-irq - 32)
34 * [0..P-1] SPIs
38 * + sysbus IRQs: (in order; number will vary depending on number of cores)
39 * - IRQ for CPU 0
[all …]
H A Dbcm2836_control.h12 * See the COPYING file in the top-level directory.
22 /* 4 mailboxes per core, for 16 total */
23 #define BCM2836_NCORES 4
24 #define BCM2836_MBPERCORE 4
26 #define TYPE_BCM2836_CONTROL "bcm2836-control"
52 /* interrupt source registers, post-routing (also input-derived; visible) */
56 /* outputs to CPU cores */
/qemu/hw/alpha/
H A Dalpha_sys.h1 /* Alpha cores and system support chips. */
6 #include "target/alpha/cpu-qom.h"
12 PCIBus *typhoon_init(MemoryRegion *, qemu_irq *, qemu_irq *, AlphaCPU *[4],
/qemu/include/hw/arm/
H A Dallwinner-h3.h21 * The Allwinner H3 is a System on Chip containing four ARM Cortex-A7
22 * processor cores. Features and specifications include DDR2/DDR3 memory,
28 * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf
32 * https://linux-sunxi.org/H3
39 #include "hw/timer/allwinner-a10-pit.h"
41 #include "hw/misc/allwinner-h3-ccu.h"
42 #include "hw/misc/allwinner-cpucfg.h"
43 #include "hw/misc/allwinner-h3-dramc.h"
44 #include "hw/misc/allwinner-h3-sysctrl.h"
45 #include "hw/misc/allwinner-sid.h"
[all …]
/qemu/tests/vm/
H A Dconf_example_x86.yml5 qemu-conf:
26 # 4 NUMA nodes and 2 different NUMA distances.
27 qemu_args: "-smp cpus=8,sockets=2,cores=4
28 -object memory-backend-ram,size=4G,policy=bind,host-nodes=0,id=ram-node0
29 -object memory-backend-ram,size=4G,policy=bind,host-nodes=0,id=ram-node1
30 -object memory-backend-ram,size=4G,policy=bind,host-nodes=1,id=ram-node2
31 -object memory-backend-ram,size=4G,policy=bind,host-nodes=1,id=ram-node3
32 -numa node,cpus=0-1,nodeid=0 -numa node,cpus=2-3,nodeid=1
33 -numa node,cpus=4-5,nodeid=2 -numa node,cpus=6-7,nodeid=3
34 -numa dist,src=0,dst=1,val=15 -numa dist,src=2,dst=3,val=15
[all …]
H A Dconf_example_aarch64.yml5 qemu-conf:
21 machine: virt,gic-version=max
25 # 4 NUMA nodes and 2 different NUMA distances.
26 qemu_args: "-smp cpus=16,sockets=2,cores=8
27 -numa node,cpus=0-3,nodeid=0 -numa node,cpus=4-7,nodeid=1
28 -numa node,cpus=8-11,nodeid=2 -numa node,cpus=12-15,nodeid=3
29 -numa dist,src=0,dst=1,val=15 -numa dist,src=2,dst=3,val=15
30 -numa dist,src=0,dst=2,val=20 -numa dist,src=0,dst=3,val=20
31 -numa dist,src=1,dst=2,val=20 -numa dist,src=1,dst=3,val=20"
48 #install_cmds: "apt-get update ; apt-get build-dep -y qemu"
/qemu/hw/loongarch/
H A Dvirt.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 #include "hw/char/serial-mm.h"
22 #include "system/address-spaces.h"
31 #include "hw/pci-host/ls7a.h"
32 #include "hw/pci-host/gpex.h"
37 #include "qapi/qapi-visit-common.h"
40 #include "hw/platform-bus.h"
42 #include "hw/uefi/var-service-api.h"
43 #include "hw/mem/pc-dimm.h"
45 #include "system/block-backend.h"
[all …]
/qemu/target/s390x/kvm/
H A Dstsi-topology.c1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include "hw/s390x/cpu-topology.h"
30 tle->nl = level; in fill_container()
31 tle->id = id; in fill_container()
46 S390TopologyId topology_id = entry->id; in fill_tle_cpu()
48 tle->nl = 0; in fill_tle_cpu()
49 tle->flags = 0; in fill_tle_cpu()
51 tle->flags |= topology_id.entitlement; in fill_tle_cpu()
54 tle->flags |= SYSIB_TLE_DEDICATED; in fill_tle_cpu()
56 tle->type = topology_id.type; in fill_tle_cpu()
[all …]
/qemu/docs/system/devices/
H A Dcan.rst22 open-source/design/hardware solution. The core designer
34 ----------------------------------------------------------
38 (1) CAN bus Kvaser PCI CAN-S (single SJA1000 channel) board. QEMU startup options::
40 -object can-bus,id=canbus0
41 -device kvaser_pci,canbus=canbus0
43 Add "can-host-socketcan" object to connect device to host system CAN bus::
45 -object can-host-socketcan,id=canhost0,if=can0,canbus=canbus0
47 (2) CAN bus PCM-3680I PCI (dual SJA1000 channel) emulation::
49 -object can-bus,id=canbus0
50 -device pcm3680_pci,canbus0=canbus0,canbus1=canbus0
[all …]

1234