hw/intc/arm_gic.h

23  *  + QOM property "num-cpu": number of CPUs to support
24  *  + QOM property "num-irq": number of IRQs (including both SPIs and PPIs)
26  *  + QOM property "has-security-extensions": set true if the GIC should
28  *  + QOM property "has-virtualization-extensions": set true if the GIC should
30  *  + QOM property "first-cpu-index": index of the first cpu attached to the
32  *    first-cpu-index, first-cpu-index + 1, ... first-cpu-index + num-cpu - 1.
33  *  + unnamed GPIO inputs: (where P is number of SPIs, i.e. num-irq - 32)
34  *    [0..P-1]  SPIs
38  *  + sysbus IRQs: (in order; number will vary depending on number of cores)
39  *    - IRQ for CPU 0
40  *    - IRQ for CPU 1
42  *    - FIQ for CPU 0
43  *    - FIQ for CPU 1
45  *    - VIRQ for CPU 0 (exists even if virt extensions not present)
46  *    - VIRQ for CPU 1 (exists even if virt extensions not present)
48  *    - VFIQ for CPU 0 (exists even if virt extensions not present)
49  *    - VFIQ for CPU 1 (exists even if virt extensions not present)
51  *    - maintenance IRQ for CPU i/f 0 (only if virt extensions present)
52  *    - maintenance IRQ for CPU i/f 1 (only if virt extensions present)
54  *    whether virtualization extensions are present and on number of cores)
55  *    - distributor registers (GICD*)
56  *    - CPU interface for the accessing core (GICC*)
57  *    - virtual interface control registers (GICH*) (only if virt extns present)
58  *    - virtual CPU interface for the accessing core (GICV*) (only if virt)
59  *    - CPU 0 CPU interface registers
60  *    - CPU 1 CPU interface registers
62  *    - CPU 0 virtual interface control registers (only if virt extns present)
63  *    - CPU 1 virtual interface control registers (only if virt extns present)
73 /* Number of SGI target-list bits */
76 #define GIC_MIN_PRIORITY_BITS 4