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/qemu/include/libdecnumber/
H A DdecDPD.h43 /* uint8_t BIN2CHAR[4001]; -- Bin -> CHAR (999 => '\3' '9' '9' '9') */
44 /* uint8_t BIN2BCD8[4000]; -- Bin -> bytes (999 => 9 9 9 3) */
49 /* uint8_t DPD2BCD8[4096]; -- DPD -> bytes (x3FF => 9 9 9 3) */
67 const uint16_t BCD2DPD[2458]={ 0, 1, 2, 3, 4, 5, 6, 7,
262 const uint16_t DPD2BCD[1024]={ 0, 1, 2, 3, 4, 5, 6, 7,
347 const uint16_t BIN2DPD[1000]={ 0, 1, 2, 3, 4, 5, 6, 7,
430 const uint16_t DPD2BIN[1024]={ 0, 1, 2, 3, 4, 5, 6, 7,
776 '\0','0','0','0', '\1','0','0','1', '\1','0','0','2', '\1','0','0','3', '\1','0','0','4',
778 '\2','0','1','0', '\2','0','1','1', '\2','0','1','2', '\2','0','1','3', '\2','0','1','4',
780 '\2','0','2','0', '\2','0','2','1', '\2','0','2','2', '\2','0','2','3', '\2','0','2','4',
[all …]
/qemu/target/mips/tcg/
H A Dmsa.decode29 %3r_df_h 21:1 !function=plus_1
30 %3r_df_w 21:1 !function=plus_2
34 @bz_v ...... ... .. wt:5 sa:s16 &msa_bz df=3
41 @3r ...... ... df:2 wt:5 ws:5 wd:5 ...... &msa_r
42 @3rf_h ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_h
43 @3rf_w ...... .... . wt:5 ws:5 wd:5 ...... &msa_r df=%3r_df_w
97 SLL 011110 000.. ..... ..... ..... 001101 @3r
98 SRA 011110 001.. ..... ..... ..... 001101 @3r
99 SRL 011110 010.. ..... ..... ..... 001101 @3r
100 BCLR 011110 011.. ..... ..... ..... 001101 @3r
[all …]
/qemu/linux-user/mips/
H A Dsyscall-args-o32.c.inc4 [ 3] = 3, /* read */
5 [ 4] = 3, /* write */
6 [ 5] = 3, /* open */
8 [ 7] = 3, /* waitpid */
12 [ 11] = 3, /* execve */
15 [ 14] = 3, /* mknod */
17 [ 16] = 3, /* lchown */
20 [ 19] = 3, /* lseek */
55 [ 54] = 3, /* ioctl */
56 [ 55] = 3, /* fcntl */
[all …]
/qemu/target/s390x/tcg/
H A Dinsn-format.h.inc8 F3(RIE_a, R(1, 8), I(2,16,16), M(3,32))
9 F4(RIE_b, R(1, 8), R(2,12), M(3,32), I(4,16,16))
10 F4(RIE_c, R(1, 8), I(2,32, 8), M(3,12), I(4,16,16))
11 F3(RIE_d, R(1, 8), I(2,16,16), R(3,12))
12 F3(RIE_e, R(1, 8), I(2,16,16), R(3,12))
13 F5(RIE_f, R(1, 8), R(2,12), I(3,16,8), I(4,24,8), I(5,32,8))
14 F3(RIE_g, R(1, 8), I(2,16,16), M(3,12))
18 F4(RIS, R(1, 8), I(2,32, 8), M(3,12), BD(4,16,20))
24 F3(RRD, R(1,16), R(2,28), R(3,24))
25 F4(RRF_a, R(1,24), R(2,28), R(3,16), M(4,20))
[all …]
/qemu/target/hexagon/idef-parser/
H A Didef-parser.y276 @1.last_column = @3.last_column;
277 gen_assign(c, &@1, &$1, &$3);
282 @1.last_column = @3.last_column;
283 gen_assign(c, &@1, &$1, &$3);
288 @1.last_column = @3.last_column;
289 HexValue tmp = gen_bin_op(c, &@1, ADD_OP, &$1, &$3);
295 @1.last_column = @3.last_column;
296 HexValue tmp = gen_bin_op(c, &@1, SUB_OP, &$1, &$3);
302 @1.last_column = @3.last_column;
303 HexValue tmp = gen_bin_op(c, &@1, ANDB_OP, &$1, &$3);
[all …]
/qemu/disas/
H A Dsparc.c136 3 SIAM mode (3 bits). (v9b)
191 #define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
363 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 },
364 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */
365 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 },
366 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 },
367 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 },
368 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */
369 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 },
370 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */
[all …]
/qemu/target/arm/tcg/
H A Dt16.decode44 %reg_0 0:3
46 @lll_noshr ...... .... rm:3 rd:3 \
48 @xll_noshr ...... .... rm:3 rn:3 \
50 @lxl_shr ...... .... rs:3 rd:3 \
60 MOV_rxrr 010000 0111 ... ... @lxl_shr shty=3 # ROR
62 RSB_rri 010000 1001 rn:3 rd:3 &s_rri_rot %s imm=0 rot=0
66 MUL 010000 1101 rn:3 rd:3 &s_rrrr %s rm=%reg_0 ra=0
72 @ldst_rr ....... rm:3 rn:3 rt:3 \
88 @ldst_ri_1 ..... imm:5 rn:3 rt:3 \
90 @ldst_ri_4 ..... ..... rn:3 rt:3 \
[all …]
H A Dneon-dp.decode36 # 3-reg-same grouping:
40 &3same vm vn vd q size
42 @3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
43 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
45 @3same_q0 .... ... . . . size:2 .... .... .... . 0 . . .... \
46 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
52 %3same_fp_size 20:1 !function=neon_3same_fp_size
54 @3same_fp .... ... . . . . . .... .... .... . q:1 . . .... \
55 &3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%3same_fp_size
56 @3same_fp_q0 .... ... . . . . . .... .... .... . 0 . . .... \
[all …]
H A Dsme.decode31 MOVA 11000000 esz:2 00000 0 v:1 .. pg:3 zr:5 0 za_imm:4 \
33 MOVA 11000000 11 00000 1 v:1 .. pg:3 zr:5 0 za_imm:4 \
36 MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0 za_imm:4 zr:5 \
38 MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \
45 LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \
47 LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \
60 @adda_32 ........ .. ..... . pm:3 pn:3 zn:5 ... zad:2 &adda
61 @adda_64 ........ .. ..... . pm:3 pn:3 zn:5 .. zad:3 &adda
71 @op_32 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 .. zad:2 &op
72 @op_64 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 . zad:3 &op
/qemu/include/hw/misc/
H A Dxlnx-zynqmp-crf.h30 FIELD(APLL_CTRL, POST_SRC, 24, 3)
31 FIELD(APLL_CTRL, PRE_SRC, 20, 3)
35 FIELD(APLL_CTRL, BYPASS, 3, 1)
45 FIELD(APLL_FRAC_CFG, SEED, 22, 3)
50 FIELD(DPLL_CTRL, POST_SRC, 24, 3)
51 FIELD(DPLL_CTRL, PRE_SRC, 20, 3)
55 FIELD(DPLL_CTRL, BYPASS, 3, 1)
65 FIELD(DPLL_FRAC_CFG, SEED, 22, 3)
70 FIELD(VPLL_CTRL, POST_SRC, 24, 3)
71 FIELD(VPLL_CTRL, PRE_SRC, 20, 3)
[all …]
H A Dxlnx-versal-crl.h34 FIELD(RPLL_CTRL, POST_SRC, 24, 3)
35 FIELD(RPLL_CTRL, PRE_SRC, 20, 3)
38 FIELD(RPLL_CTRL, BYPASS, 3, 1)
48 FIELD(RPLL_FRAC_CFG, SEED, 22, 3)
62 FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3)
66 FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3)
73 FIELD(CPU_R5_CTRL, SRCSEL, 0, 3)
77 FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3)
83 FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3)
89 FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3)
[all …]
/qemu/tests/unit/
H A Dtest-x86-topo.c47 g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 3), ==, 3); in test_topo_bits()
54 topo_info = (X86CPUTopoInfo) {1, 1, 1, 3}; in test_topo_bits()
79 g_assert_cmpuint(apicid_module_width(&topo_info), ==, 3); in test_topo_bits()
81 g_assert_cmpuint(apicid_module_width(&topo_info), ==, 3); in test_topo_bits()
83 g_assert_cmpuint(apicid_module_width(&topo_info), ==, 3); in test_topo_bits()
91 topo_info = (X86CPUTopoInfo) {3, 6, 30, 2}; in test_topo_bits()
99 /* This will use 2 bits for thread ID and 3 bits for core ID in test_topo_bits()
101 topo_info = (X86CPUTopoInfo) {1, 1, 6, 3}; in test_topo_bits()
108 topo_info = (X86CPUTopoInfo) {1, 1, 6, 3}; in test_topo_bits()
113 topo_info = (X86CPUTopoInfo) {1, 1, 6, 3}; in test_topo_bits()
[all …]
/qemu/target/xtensa/
H A Dxtensa-semi.c40 TARGET_SYS_read = 3,
56 SELECT_ONE_EXCEPT = 3,
62 TARGET_ESRCH = 3,
200 exit(regs[3]); in HELPER()
207 uint32_t fd = regs[3]; in HELPER()
225 if (fd < 3 && sim_console) { in HELPER()
229 regs[3] = errno_h2g(errno); in HELPER()
244 regs[3] = TARGET_EAGAIN; in HELPER()
252 regs[3] = TARGET_EBADF; in HELPER()
258 regs[3] = errno_h2g(errno); in HELPER()
[all …]
/qemu/hw/misc/
H A Dxlnx-versal-pmc-iou-slcr.c41 FIELD(MIO_PIN_0, L3_SEL, 7, 3)
43 FIELD(MIO_PIN_0, L1_SEL, 3, 2)
46 FIELD(MIO_PIN_1, L3_SEL, 7, 3)
48 FIELD(MIO_PIN_1, L1_SEL, 3, 2)
51 FIELD(MIO_PIN_2, L3_SEL, 7, 3)
53 FIELD(MIO_PIN_2, L1_SEL, 3, 2)
56 FIELD(MIO_PIN_3, L3_SEL, 7, 3)
58 FIELD(MIO_PIN_3, L1_SEL, 3, 2)
61 FIELD(MIO_PIN_4, L3_SEL, 7, 3)
63 FIELD(MIO_PIN_4, L1_SEL, 3, 2)
[all …]
/qemu/host/include/loongarch64/host/
H A Dbufferiszero.c.inc22 "vld $vr2,%3,0\n\t" /* e[0] */
23 "vld $vr3,%3,16\n\t" /* e[1] */
24 "vld $vr4,%3,32\n\t" /* e[2] */
25 "vld $vr5,%3,48\n\t" /* e[3] */
26 "vld $vr6,%3,64\n\t" /* e[4] */
27 "vld $vr7,%3,80\n\t" /* e[5] */
28 "vld $vr8,%3,96\n\t" /* e[6] */
44 "vld $vr3,%1,48\n\t" /* p[3] */
57 "bltu %1,%3,1b\n\t"
79 "xvld $xr2,%3,0\n\t" /* e[0] */
[all …]
/qemu/linux-headers/asm-arm64/
H A Dkvm.h30 #define KVM_SPSR_IRQ 3
65 #define KVM_ARM_TARGET_XGENE_POTENZA 3
92 #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
103 #define KVM_ARM_VCPU_PMU_V3 3 /* Support guest PMUv3 */
122 * See v8 ARM ARM D7.3: Debug Registers
178 __u8 pad[3];
239 #define KVM_REG_ARM64_SYSREG_CRM_SHIFT 3
258 #define KVM_REG_ARM_PTIMER_CTL ARM64_SYS_REG(3, 3, 14, 2, 1)
259 #define KVM_REG_ARM_PTIMER_CVAL ARM64_SYS_REG(3, 3, 14, 2, 2)
260 #define KVM_REG_ARM_PTIMER_CNT ARM64_SYS_REG(3, 3, 14, 0, 1)
[all …]
/qemu/target/arm/hvf/
H A Dhvf.c187 #define SYSREG_OSDLR_EL1 SYSREG(2, 0, 1, 3, 4)
188 #define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1)
189 #define SYSREG_CNTP_CTL_EL0 SYSREG(3, 3, 14, 2, 1)
190 #define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0)
191 #define SYSREG_PMUSERENR_EL0 SYSREG(3, 3, 9, 14, 0)
192 #define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1)
193 #define SYSREG_PMCNTENCLR_EL0 SYSREG(3, 3, 9, 12, 2)
194 #define SYSREG_PMINTENCLR_EL1 SYSREG(3, 0, 9, 14, 2)
195 #define SYSREG_PMOVSCLR_EL0 SYSREG(3, 3, 9, 12, 3)
196 #define SYSREG_PMSWINC_EL0 SYSREG(3, 3, 9, 12, 4)
[all …]
/qemu/include/ui/
H A Dpixel_ops.h10 return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3); in rgb_to_pixel15()
16 return ((b >> 3) << 10) | ((g >> 3) << 5) | (r >> 3); in rgb_to_pixel15bgr()
22 return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3); in rgb_to_pixel16()
28 return ((b >> 3) << 11) | ((g >> 2) << 5) | (r >> 3); in rgb_to_pixel16bgr()
/qemu/hw/net/
H A Dtulip.h11 #define CSR(_x) ((_x) << 3)
35 #define CSR5_TJT BIT(3)
57 #define CSR5_TS_RUNNING_READ_BUF 3
65 #define CSR5_RS_RUNNING_WAIT_RECEIVE 3
80 #define CSR6_PB BIT(3)
89 #define CSR6_OM_MASK 3
99 #define CSR6_TR_MASK 3
103 #define CSR6_TR_160 3
112 #define CSR7_TJM BIT(3)
133 #define CSR9_SR_DO BIT(3)
[all …]
/qemu/hw/sparc64/
H A Dsun4u_iommu.c91 if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) { in sun4u_translate_iommu()
101 baseaddr = is->regs[IOMMU_BASE >> 3]; in sun4u_translate_iommu()
102 tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7; in sun4u_translate_iommu()
104 if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) { in sun4u_translate_iommu()
116 case 3: in sun4u_translate_iommu()
141 case 3: in sun4u_translate_iommu()
202 is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL; in iommu_mem_write()
203 is->regs[IOMMU_CTRL >> 3] |= val << 32; in iommu_mem_write()
205 is->regs[IOMMU_CTRL >> 3] = val; in iommu_mem_write()
209 is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL; in iommu_mem_write()
[all …]
/qemu/tests/tcg/s390x/
H A Dlcbb.c17 *cc = (*cc >> 28) & 3; in lcbb()
36 test_lcbb(&buf[63], 0, 1, 3); in main()
38 test_lcbb(&buf[127], 1, 1, 3); in main()
40 test_lcbb(&buf[255], 2, 1, 3); in main()
41 test_lcbb(&buf[0], 3, 16, 0); in main()
42 test_lcbb(&buf[511], 3, 1, 3); in main()
44 test_lcbb(&buf[1023], 4, 1, 3); in main()
46 test_lcbb(&buf[2047], 5, 1, 3); in main()
48 test_lcbb(&buf[4095], 6, 1, 3); in main()
H A Dsam.S41 /* DT = 0b11 (region-first-table), TL = 3 (2k entries) */
42 .quad region_first_table + (3 << 2) + 3
46 /* TT = 0b11 (region-first-table), TL = 3 (2k entries) */
47 .quad region_second_table + (3 << 2) + 3
51 /* TT = 0b10 (region-second-table), TL = 3 (2k entries) */
52 .quad region_third_table + (2 << 2) + 3
56 /* TT = 0b01 (region-third-table), TL = 3 (2k entries) */
57 .quad segment_table + (1 << 2) + 3
/qemu/rust/qemu-api/tests/
H A Dvmstate_tests.rs24 const FOO_ARRAY_MAX: usize = 3;
101 // 3rd VMStateField ("arr") in VMSTATE_FOOA (corresponding to in test_vmstate_varray_uint16_unsafe()
125 unsafe { CStr::from_ptr(foo_fields[3].name) }.to_bytes_with_nul(), in test_vmstate_varray_multiply()
128 assert_eq!(foo_fields[3].offset, 6); in test_vmstate_varray_multiply()
129 assert_eq!(foo_fields[3].num_offset, 12); in test_vmstate_varray_multiply()
130 assert_eq!(foo_fields[3].info, unsafe { &vmstate_info_int8 }); in test_vmstate_varray_multiply()
131 assert_eq!(foo_fields[3].version_id, 0); in test_vmstate_varray_multiply()
132 assert_eq!(foo_fields[3].size, 1); in test_vmstate_varray_multiply()
133 assert_eq!(foo_fields[3].num, 16); in test_vmstate_varray_multiply()
135 foo_fields[3].flags.0, in test_vmstate_varray_multiply()
[all …]
/qemu/hw/net/can/
H A Dctu_can_fd_regs.h492 uint32_t reserved_31_29 : 3;
494 uint32_t reserved_31_29 : 3;
506 uint32_t reserved_31_29 : 3;
508 uint32_t reserved_31_29 : 3;
520 uint32_t reserved_31_29 : 3;
522 uint32_t reserved_31_29 : 3;
534 uint32_t reserved_31_29 : 3;
536 uint32_t reserved_31_29 : 3;
548 uint32_t reserved_31_29 : 3;
550 uint32_t reserved_31_29 : 3;
[all …]
/qemu/tests/decode/
H A Dsucc_ident1.decode3 %3f 16:8
5 &3arg a b c
6 @3arg ........ ........ ........ ........ &3arg a=%1f b=%2f c=%3f
7 3insn 00000000 ........ ........ ........ @3arg

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