1*9da8320bSMax Filippov /* 2*9da8320bSMax Filippov * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration 3*9da8320bSMax Filippov * 4*9da8320bSMax Filippov * NOTE: This header file is not meant to be included directly. 5*9da8320bSMax Filippov */ 6*9da8320bSMax Filippov 7*9da8320bSMax Filippov /* This header file describes this specific Xtensa processor's TIE extensions 8*9da8320bSMax Filippov that extend basic Xtensa core functionality. It is customized to this 9*9da8320bSMax Filippov Xtensa processor configuration. 10*9da8320bSMax Filippov 11*9da8320bSMax Filippov Copyright (c) 1999-2014 Tensilica Inc. 12*9da8320bSMax Filippov 13*9da8320bSMax Filippov Permission is hereby granted, free of charge, to any person obtaining 14*9da8320bSMax Filippov a copy of this software and associated documentation files (the 15*9da8320bSMax Filippov "Software"), to deal in the Software without restriction, including 16*9da8320bSMax Filippov without limitation the rights to use, copy, modify, merge, publish, 17*9da8320bSMax Filippov distribute, sublicense, and/or sell copies of the Software, and to 18*9da8320bSMax Filippov permit persons to whom the Software is furnished to do so, subject to 19*9da8320bSMax Filippov the following conditions: 20*9da8320bSMax Filippov 21*9da8320bSMax Filippov The above copyright notice and this permission notice shall be included 22*9da8320bSMax Filippov in all copies or substantial portions of the Software. 23*9da8320bSMax Filippov 24*9da8320bSMax Filippov THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25*9da8320bSMax Filippov EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26*9da8320bSMax Filippov MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 27*9da8320bSMax Filippov IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 28*9da8320bSMax Filippov CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 29*9da8320bSMax Filippov TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 30*9da8320bSMax Filippov SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 31*9da8320bSMax Filippov 32*9da8320bSMax Filippov #ifndef _XTENSA_CORE_TIE_H 33*9da8320bSMax Filippov #define _XTENSA_CORE_TIE_H 34*9da8320bSMax Filippov 35*9da8320bSMax Filippov #define XCHAL_CP_NUM 2 /* number of coprocessors */ 36*9da8320bSMax Filippov #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */ 37*9da8320bSMax Filippov #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */ 38*9da8320bSMax Filippov #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */ 39*9da8320bSMax Filippov 40*9da8320bSMax Filippov /* Basic parameters of each coprocessor: */ 41*9da8320bSMax Filippov #define XCHAL_CP1_NAME "AudioEngineLX" 42*9da8320bSMax Filippov #define XCHAL_CP1_IDENT AudioEngineLX 43*9da8320bSMax Filippov #define XCHAL_CP1_SA_SIZE 184 /* size of state save area */ 44*9da8320bSMax Filippov #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */ 45*9da8320bSMax Filippov #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */ 46*9da8320bSMax Filippov #define XCHAL_CP7_NAME "XTIOP" 47*9da8320bSMax Filippov #define XCHAL_CP7_IDENT XTIOP 48*9da8320bSMax Filippov #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */ 49*9da8320bSMax Filippov #define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */ 50*9da8320bSMax Filippov #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */ 51*9da8320bSMax Filippov 52*9da8320bSMax Filippov /* Filler info for unassigned coprocessors, to simplify arrays etc: */ 53*9da8320bSMax Filippov #define XCHAL_CP0_SA_SIZE 0 54*9da8320bSMax Filippov #define XCHAL_CP0_SA_ALIGN 1 55*9da8320bSMax Filippov #define XCHAL_CP2_SA_SIZE 0 56*9da8320bSMax Filippov #define XCHAL_CP2_SA_ALIGN 1 57*9da8320bSMax Filippov #define XCHAL_CP3_SA_SIZE 0 58*9da8320bSMax Filippov #define XCHAL_CP3_SA_ALIGN 1 59*9da8320bSMax Filippov #define XCHAL_CP4_SA_SIZE 0 60*9da8320bSMax Filippov #define XCHAL_CP4_SA_ALIGN 1 61*9da8320bSMax Filippov #define XCHAL_CP5_SA_SIZE 0 62*9da8320bSMax Filippov #define XCHAL_CP5_SA_ALIGN 1 63*9da8320bSMax Filippov #define XCHAL_CP6_SA_SIZE 0 64*9da8320bSMax Filippov #define XCHAL_CP6_SA_ALIGN 1 65*9da8320bSMax Filippov 66*9da8320bSMax Filippov /* Save area for non-coprocessor optional and custom (TIE) state: */ 67*9da8320bSMax Filippov #define XCHAL_NCP_SA_SIZE 36 68*9da8320bSMax Filippov #define XCHAL_NCP_SA_ALIGN 4 69*9da8320bSMax Filippov 70*9da8320bSMax Filippov /* Total save area for optional and custom state (NCP + CPn): */ 71*9da8320bSMax Filippov #define XCHAL_TOTAL_SA_SIZE 240 /* with 16-byte align padding */ 72*9da8320bSMax Filippov #define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */ 73*9da8320bSMax Filippov 74*9da8320bSMax Filippov /* 75*9da8320bSMax Filippov * Detailed contents of save areas. 76*9da8320bSMax Filippov * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) 77*9da8320bSMax Filippov * before expanding the XCHAL_xxx_SA_LIST() macros. 78*9da8320bSMax Filippov * 79*9da8320bSMax Filippov * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, 80*9da8320bSMax Filippov * dbnum,base,regnum,bitsz,gapsz,reset,x...) 81*9da8320bSMax Filippov * 82*9da8320bSMax Filippov * s = passed from XCHAL_*_LIST(s), eg. to select how to expand 83*9da8320bSMax Filippov * ccused = set if used by compiler without special options or code 84*9da8320bSMax Filippov * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) 85*9da8320bSMax Filippov * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) 86*9da8320bSMax Filippov * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) 87*9da8320bSMax Filippov * name = lowercase reg name (no quotes) 88*9da8320bSMax Filippov * galign = group byte alignment (power of 2) (galign >= align) 89*9da8320bSMax Filippov * align = register byte alignment (power of 2) 90*9da8320bSMax Filippov * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) 91*9da8320bSMax Filippov * (not including any pad bytes required to galign this or next reg) 92*9da8320bSMax Filippov * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>) 93*9da8320bSMax Filippov * base = reg shortname w/o index (or sr=special, ur=TIE user reg) 94*9da8320bSMax Filippov * regnum = reg index in regfile, or special/TIE-user reg number 95*9da8320bSMax Filippov * bitsz = number of significant bits (regfile width, or ur/sr mask bits) 96*9da8320bSMax Filippov * gapsz = intervening bits, if bitsz bits not stored contiguously 97*9da8320bSMax Filippov * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) 98*9da8320bSMax Filippov * reset = register reset value (or 0 if undefined at reset) 99*9da8320bSMax Filippov * x = reserved for future use (0 until then) 100*9da8320bSMax Filippov * 101*9da8320bSMax Filippov * To filter out certain registers, e.g. to expand only the non-global 102*9da8320bSMax Filippov * registers used by the compiler, you can do something like this: 103*9da8320bSMax Filippov * 104*9da8320bSMax Filippov * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) 105*9da8320bSMax Filippov * #define SELCC0(p...) 106*9da8320bSMax Filippov * #define SELCC1(abikind,p...) SELAK##abikind(p) 107*9da8320bSMax Filippov * #define SELAK0(p...) REG(p) 108*9da8320bSMax Filippov * #define SELAK1(p...) REG(p) 109*9da8320bSMax Filippov * #define SELAK2(p...) 110*9da8320bSMax Filippov * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ 111*9da8320bSMax Filippov * ...what you want to expand... 112*9da8320bSMax Filippov */ 113*9da8320bSMax Filippov 114*9da8320bSMax Filippov #define XCHAL_NCP_SA_NUM 9 115*9da8320bSMax Filippov #define XCHAL_NCP_SA_LIST(s) \ 116*9da8320bSMax Filippov XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ 117*9da8320bSMax Filippov XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ 118*9da8320bSMax Filippov XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ 119*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ 120*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ 121*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ 122*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \ 123*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ 124*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) 125*9da8320bSMax Filippov 126*9da8320bSMax Filippov #define XCHAL_CP0_SA_NUM 0 127*9da8320bSMax Filippov #define XCHAL_CP0_SA_LIST(s) /* empty */ 128*9da8320bSMax Filippov 129*9da8320bSMax Filippov #define XCHAL_CP1_SA_NUM 26 130*9da8320bSMax Filippov #define XCHAL_CP1_SA_LIST(s) \ 131*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 8,0,0,0) \ 132*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \ 133*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \ 134*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,1,0, ae_cw_sd_no, 4, 4, 4,0x03F3, ur,243, 29,0,0,0) \ 135*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,1,0, ae_cbegin0, 4, 4, 4,0x03F6, ur,246, 32,0,0,0) \ 136*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,1,0, ae_cend0, 4, 4, 4,0x03F7, ur,247, 32,0,0,0) \ 137*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed0, 8, 8, 8,0x1010, aed,0 , 64,0,0,0) \ 138*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed1, 8, 8, 8,0x1011, aed,1 , 64,0,0,0) \ 139*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed2, 8, 8, 8,0x1012, aed,2 , 64,0,0,0) \ 140*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed3, 8, 8, 8,0x1013, aed,3 , 64,0,0,0) \ 141*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed4, 8, 8, 8,0x1014, aed,4 , 64,0,0,0) \ 142*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed5, 8, 8, 8,0x1015, aed,5 , 64,0,0,0) \ 143*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed6, 8, 8, 8,0x1016, aed,6 , 64,0,0,0) \ 144*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed7, 8, 8, 8,0x1017, aed,7 , 64,0,0,0) \ 145*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed8, 8, 8, 8,0x1018, aed,8 , 64,0,0,0) \ 146*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed9, 8, 8, 8,0x1019, aed,9 , 64,0,0,0) \ 147*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed10, 8, 8, 8,0x101A, aed,10 , 64,0,0,0) \ 148*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed11, 8, 8, 8,0x101B, aed,11 , 64,0,0,0) \ 149*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed12, 8, 8, 8,0x101C, aed,12 , 64,0,0,0) \ 150*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed13, 8, 8, 8,0x101D, aed,13 , 64,0,0,0) \ 151*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed14, 8, 8, 8,0x101E, aed,14 , 64,0,0,0) \ 152*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, aed15, 8, 8, 8,0x101F, aed,15 , 64,0,0,0) \ 153*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, u0, 8, 8, 8,0x1020, u,0 , 64,0,0,0) \ 154*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, u1, 8, 8, 8,0x1021, u,1 , 64,0,0,0) \ 155*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, u2, 8, 8, 8,0x1022, u,2 , 64,0,0,0) \ 156*9da8320bSMax Filippov XCHAL_SA_REG(s,0,0,2,0, u3, 8, 8, 8,0x1023, u,3 , 64,0,0,0) 157*9da8320bSMax Filippov 158*9da8320bSMax Filippov #define XCHAL_CP2_SA_NUM 0 159*9da8320bSMax Filippov #define XCHAL_CP2_SA_LIST(s) /* empty */ 160*9da8320bSMax Filippov 161*9da8320bSMax Filippov #define XCHAL_CP3_SA_NUM 0 162*9da8320bSMax Filippov #define XCHAL_CP3_SA_LIST(s) /* empty */ 163*9da8320bSMax Filippov 164*9da8320bSMax Filippov #define XCHAL_CP4_SA_NUM 0 165*9da8320bSMax Filippov #define XCHAL_CP4_SA_LIST(s) /* empty */ 166*9da8320bSMax Filippov 167*9da8320bSMax Filippov #define XCHAL_CP5_SA_NUM 0 168*9da8320bSMax Filippov #define XCHAL_CP5_SA_LIST(s) /* empty */ 169*9da8320bSMax Filippov 170*9da8320bSMax Filippov #define XCHAL_CP6_SA_NUM 0 171*9da8320bSMax Filippov #define XCHAL_CP6_SA_LIST(s) /* empty */ 172*9da8320bSMax Filippov 173*9da8320bSMax Filippov #define XCHAL_CP7_SA_NUM 0 174*9da8320bSMax Filippov #define XCHAL_CP7_SA_LIST(s) /* empty */ 175*9da8320bSMax Filippov 176*9da8320bSMax Filippov /* Byte length of instruction from its first nibble (op0 field), per FLIX. */ 177*9da8320bSMax Filippov #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8 178*9da8320bSMax Filippov /* Byte length of instruction from its first byte, per FLIX. */ 179*9da8320bSMax Filippov #define XCHAL_BYTE0_FORMAT_LENGTHS \ 180*9da8320bSMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ 181*9da8320bSMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ 182*9da8320bSMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ 183*9da8320bSMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ 184*9da8320bSMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ 185*9da8320bSMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ 186*9da8320bSMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ 187*9da8320bSMax Filippov 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8 188*9da8320bSMax Filippov 189*9da8320bSMax Filippov #endif /*_XTENSA_CORE_TIE_H*/ 190