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/qemu/hw/misc/
H A Darm_sysctl.c110 s->mb_clock[2] = 24000000; /* IO FPGA peripheral clock: 24MHz */ in arm_sysctl_reset()
111 s->mb_clock[3] = 24000000; /* IO FPGA reserved clock: 24MHz */ in arm_sysctl_reset()
112 s->mb_clock[4] = 24000000; /* System bus global clock: 24MHz */ in arm_sysctl_reset()
113 s->mb_clock[5] = 24000000; /* IO FPGA reserved clock: 24MHz */ in arm_sysctl_reset()
178 return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24000000, in arm_sysctl_read()
H A Dimx6_ccm.c232 #define CKIH_FREQ 24000000 /* 24MHz crystal input */
247 uint64_t freq = 24000000; in imx6_analog_get_pll2_clk()
365 freq = 24000000; in imx6_ccm_get_clock_frequency()
368 freq = 24000000 / 8; in imx6_ccm_get_clock_frequency()
H A Dimx25_ccm.c98 #define CKIH_FREQ 24000000 /* 24MHz crystal input */
H A Dimx7_ccm.c21 #define CKIH_FREQ 24000000 /* 24MHz crystal input */
H A Dimx6ul_ccm.c282 #define CKIH_FREQ 24000000 /* 24MHz crystal input */
H A Daspeed_scu.c459 return 24000000; in aspeed_scu_get_clkin()
H A Dstm32l4x5_rcc.c392 4000000, 8000000, 16000000, 24000000, 32000000, 48000000 in rcc_update_msi()
/qemu/hw/arm/
H A Dstm32vldiscovery.c38 #define SYSCLK_FRQ 24000000ULL
H A Dcubieboard.c70 if (!object_property_set_int(OBJECT(&a10->timer), "clk1-freq", 24000000, in cubieboard_init()
H A Dmps3r.c192 24000000, /* 24MHz reference for RTC and timers */
H A Dmps2-tz.c201 24000000,
H A Dvirt.c323 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); in create_fdt()
/qemu/hw/timer/
H A Dexynos4210_pwm.c161 s->timer[id].freq = 24000000 / in exynos4210_pwm_update_freq()
165 s->timer[id].freq = 24000000 / in exynos4210_pwm_update_freq()
H A Dexynos4210_mct.c1004 s->freq = 24000000 / in exynos4210_mct_update_freq()
/qemu/hw/watchdog/
H A Dwdt_aspeed.c282 #define PCLK_HZ 24000000
/qemu/hw/char/
H A Dexynos4210_uart.c370 uclk_rate = 24000000; in exynos4210_uart_update_parameters()
/qemu/include/libdecnumber/
H A DdecDPD.h628 21000000, 22000000, 23000000, 24000000, 25000000, 26000000, 27000000,