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/qemu/include/hw/misc/macio/
H A Dpmu.h72 #define PMU_INT_TICK 0x80 /* 1-second tick interrupt */
85 #define PMU_I2C_MODE_STDSUB 1
89 #define PMU_I2C_BUS_SYSCLK 1
93 #define PMU_I2C_STATUS_DATAREAD 1
103 PMU_68K_V1, /* 68K PMU, version 1 */
128 * - the number of data bytes to be sent with the command, or -1
131 * -1 if it will send a length byte.
135 /* 0 1 2 3 4 5 6 7 */
136 {-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},{-1, 0},
137 {-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},{-1, -1},
[all …]
/qemu/target/arm/tcg/
H A Dmve.decode22 %qd 22:1 13:3
23 %qm 5:1 1:3
24 %qn 7:1 17:3
26 # VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit
27 %size_28 28:1 !function=plus_1
29 # 2 operand fp insns have size in bit 20: 1 for 16 bit, 0 for 32 bit,
31 %2op_fp_size 20:1 !function=neon_3same_fp_size
32 # VCADD is an exception, where bit 20 is 0 for 16 bit and 1 for 32 bit
33 %2op_fp_size_rev 20:1 !function=plus_1
34 # FP scalars have size in bit 28, 1 for 16 bit, 0 for 32 bit
[all …]
H A Dneon-dp.decode22 %vm_dp 5:1 0:4
23 %vn_dp 7:1 16:4
24 %vd_dp 22:1 12:4
42 @3same .... ... . . . size:2 .... .... .... . q:1 . . .... \
49 # and the 'size' bit is 0 for 32-bit float and 1 for 16-bit float.
52 %3same_fp_size 20:1 !function=neon_3same_fp_size
54 @3same_fp .... ... . . . . . .... .... .... . q:1 . . .... \
60 VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
61 VQADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 1 .... @3same
62 VQADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 1 .... @3same
[all …]
/qemu/include/tcg/
H A Dtcg-opc.h30 DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
31 DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
36 DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
39 DEF(mb, 0, 0, 1, TCG_OPF_NOT_PRESENT)
41 DEF(mov, 1, 1, 0, TCG_OPF_INT | TCG_OPF_NOT_PRESENT)
43 DEF(add, 1, 2, 0, TCG_OPF_INT)
44 DEF(and, 1, 2, 0, TCG_OPF_INT)
45 DEF(andc, 1, 2, 0, TCG_OPF_INT)
46 DEF(bswap16, 1, 1, 1, TCG_OPF_INT)
47 DEF(bswap32, 1, 1, 1, TCG_OPF_INT)
[all …]
/qemu/target/hexagon/imported/mmvec/
H A Dencode_ext.def24 DEF_ENC(V6_extractw, ICLASS_LD" 001 0 000sssss PP0uuuuu --1ddddd") /* coproc insn, returns Rd */
32 DEF_CLASS32(ICLASS_NCJ" 1--- -------- PP------ --------",COPROC_VMEM)
34 DEF_CLASS32(ICLASS_NCJ" 1000 1-0ttttt PPivviii ---ddddd",BaseOffset_if_Pv_VMEM_Loads)
35 DEF_CLASS32(ICLASS_NCJ" 1000 0-1ttttt PPi--iii --------",BaseOffset_VMEM_Stores1)
36 DEF_CLASS32(ICLASS_NCJ" 1000 1-0ttttt PPi--iii 00------",BaseOffset_VMEM_Stores2)
37 DEF_CLASS32(ICLASS_NCJ" 1000 1-1ttttt PPivviii --------",BaseOffset_if_Pv_VMEM_Stores)
40 DEF_CLASS32(ICLASS_NCJ" 1001 1-0xxxxx PP-vviii ---ddddd",PostImm_if_Pv_VMEM_Loads)
41 DEF_CLASS32(ICLASS_NCJ" 1001 0-1xxxxx PP---iii --------",PostImm_VMEM_Stores1)
42 DEF_CLASS32(ICLASS_NCJ" 1001 1-0xxxxx PP---iii 00------",PostImm_VMEM_Stores2)
43 DEF_CLASS32(ICLASS_NCJ" 1001 1-1xxxxx PP-vviii --------",PostImm_if_Pv_VMEM_Stores)
[all …]
/qemu/chardev/
H A Dbaum.c91 #define Y_MAX 1
135 DO(BRLAPI_DOTS(1, 0, 0, 0, 0, 0, 0, 0), 'a'),
136 DO(BRLAPI_DOTS(1, 1, 0, 0, 0, 0, 0, 0), 'b'),
137 DO(BRLAPI_DOTS(1, 0, 0, 1, 0, 0, 0, 0), 'c'),
138 DO(BRLAPI_DOTS(1, 0, 0, 1, 1, 0, 0, 0), 'd'),
139 DO(BRLAPI_DOTS(1, 0, 0, 0, 1, 0, 0, 0), 'e'),
140 DO(BRLAPI_DOTS(1, 1, 0, 1, 0, 0, 0, 0), 'f'),
141 DO(BRLAPI_DOTS(1, 1, 0, 1, 1, 0, 0, 0), 'g'),
142 DO(BRLAPI_DOTS(1, 1, 0, 0, 1, 0, 0, 0), 'h'),
143 DO(BRLAPI_DOTS(0, 1, 0, 1, 0, 0, 0, 0), 'i'),
[all …]
/qemu/include/hw/misc/
H A Dxlnx-versal-cfu.h11 * [1] Versal ACAP Technical Reference Manual,
35 FIELD(CFU_ISR, USR_GTS_EVENT, 9, 1)
36 FIELD(CFU_ISR, USR_GSR_EVENT, 8, 1)
37 FIELD(CFU_ISR, SLVERR, 7, 1)
38 FIELD(CFU_ISR, DECOMP_ERROR, 6, 1)
39 FIELD(CFU_ISR, BAD_CFI_PACKET, 5, 1)
40 FIELD(CFU_ISR, AXI_ALIGN_ERROR, 4, 1)
41 FIELD(CFU_ISR, CFI_ROW_ERROR, 3, 1)
42 FIELD(CFU_ISR, CRC32_ERROR, 2, 1)
43 FIELD(CFU_ISR, CRC8_ERROR, 1, 1)
[all …]
H A Dxlnx-versal-cframe-reg.h11 * [1] Versal ACAP Technical Reference Manual,
36 * 1, 2, 3).
75 FIELD(CTL, PER_FRAME_CRC, 0, 1)
80 FIELD(CFRM_ISR0, READ_BROADCAST_ERROR, 21, 1)
81 FIELD(CFRM_ISR0, CMD_MISSING_ERROR, 20, 1)
82 FIELD(CFRM_ISR0, RW_ROWOFF_ERROR, 19, 1)
83 FIELD(CFRM_ISR0, READ_REG_ADDR_ERROR, 18, 1)
84 FIELD(CFRM_ISR0, READ_BLK_TYPE_ERROR, 17, 1)
85 FIELD(CFRM_ISR0, READ_FRAME_ADDR_ERROR, 16, 1)
86 FIELD(CFRM_ISR0, WRITE_REG_ADDR_ERROR, 15, 1)
[all …]
H A Dxlnx-zynqmp-crf.h18 FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
20 FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
22 FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
24 FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
26 FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
28 FIELD(CRF_WPROT, ACTIVE, 0, 1)
32 FIELD(APLL_CTRL, CLKOUTDIV, 17, 1)
33 FIELD(APLL_CTRL, DIV2, 16, 1)
35 FIELD(APLL_CTRL, BYPASS, 3, 1)
36 FIELD(APLL_CTRL, RESET, 0, 1)
[all …]
H A Dxlnx-versal-crl.h20 FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
22 FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
24 FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
26 FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
28 FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
30 FIELD(WPROT, ACTIVE, 0, 1)
32 FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1)
38 FIELD(RPLL_CTRL, BYPASS, 3, 1)
39 FIELD(RPLL_CTRL, RESET, 0, 1)
47 FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1)
[all …]
/qemu/hw/intc/
H A Dxlnx-pmu-iomod-intc.c48 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
55 FIELD(GPO0, DISABLE_RST_FTSM, 12, 1)
56 FIELD(GPO0, RST_FTSM, 11, 1)
57 FIELD(GPO0, CLR_FTSTS, 10, 1)
58 FIELD(GPO0, RST_ON_SLEEP, 9, 1)
59 FIELD(GPO0, DISABLE_TRACE_COMP, 8, 1)
60 FIELD(GPO0, PIT3_PRESCALE, 7, 1)
63 FIELD(GPO0, PIT0_PRESCALE, 1, 2)
64 FIELD(GPO0, DEBUG_REMAP, 0, 1)
66 FIELD(GPO1, MIO_5, 5, 1)
[all …]
/qemu/hw/audio/
H A Dpl041.h41 #define TXCIE (1 << 0)
42 #define RXTIE (1 << 1)
43 #define TXIE (1 << 2)
44 #define RXIE (1 << 3)
45 #define RXOIE (1 << 4)
46 #define TXUIE (1 << 5)
47 #define RXTOIE (1 << 6)
50 #define TXEN (1 << 0)
51 #define TXSLOT1 (1 << 1)
52 #define TXSLOT2 (1 << 2)
[all …]
/qemu/target/hexagon/idef-parser/
H A Didef-parser.y50 %expect 1
114 gen_inst(c, $1);
123 gen_inst_code(c, &@1);
140 track_string(c, $1.var.name);
141 $$ = $1;
169 yyassert(c, &@1, $1.bit_width <= 64,
171 $$ = $1;
211 gen_varid_allocate(c, &@1, &$2, $1.bit_width, $1.signedness);
215 $$.signedness = $1.signedness;
216 $$.bit_width = $1.bit_width;
[all …]
/qemu/tests/tcg/xtensa/
H A Dtest_b.S8 bnone a2, a3, 1f
10 1:
12 bnone a2, a3, 1f
14 1:
22 beq a2, a3, 1f
24 1:
25 movi a2, 1
26 beq a2, a3, 1f
28 1:
36 blt a2, a3, 1f
[all …]
H A Dtest_loop.S10 loop a3, 1f
11 addi a2, a2, 1
12 1:
18 loop a2, 1f
20 assert eqi, a2, -1
21 j 1f
22 1:
28 loop a3, 1f
29 addi a2, a2, 1
30 j 1f
[all …]
H A Dtest_dfp0_arith.S29 movi a2, 1
39 /* 1 + +inf = +inf */
51 /* 1 + QNaN = QNaN */
52 test_op2 add.d, f9, f10, f11, F64_1, F64_QNAN(1), \
53 F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
55 /* 1 + SNaN = QNaN */
56 test_op2 add.d, f12, f13, f14, F64_1, F64_SNAN(1), \
57 F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
61 test_op2 add.d, f15, f0, f1, F64_SNAN(1), F64_SNAN(2), \
62 F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
[all …]
H A Dtest_bi.S7 beqi a2, 7, 1f
9 1:
10 movi a2, 1
11 beqi a2, 7, 1f
13 1:
19 movi a2, 1
20 bnei a2, 7, 1f
22 1:
24 bnei a2, 7, 1f
26 1:
[all …]
/qemu/target/mips/
H A Dcpu-defs.c.inc25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
31 ((1U << CP0C1_M) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
38 ((1U << CP0C2_M))
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
63 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
64 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
85 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
86 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
87 (1 << CP0C1_CA),
[all …]
/qemu/include/hw/net/
H A Dimx_fec.h38 #define ENET_EIR 1
98 #define ENET_INT_HB (1 << 31)
99 #define ENET_INT_BABR (1 << 30)
100 #define ENET_INT_BABT (1 << 29)
101 #define ENET_INT_GRA (1 << 28)
102 #define ENET_INT_TXF (1 << 27)
103 #define ENET_INT_TXB (1 << 26)
104 #define ENET_INT_RXF (1 << 25)
105 #define ENET_INT_RXB (1 << 24)
106 #define ENET_INT_MII (1 << 23)
[all …]
/qemu/tests/qemu-iotests/
H A D261.out9 ID: 1
12 [1]
31 ID: 1
37 [1]
66 ID: 1
72 [1]
93 ID: 1
99 [1]
135 [1]
147 ID: 1
[all …]
/qemu/hw/net/can/
H A Dctu_can_fd_regs.h128 uint32_t rst : 1;
129 uint32_t lom : 1;
130 uint32_t stm : 1;
131 uint32_t afm : 1;
132 uint32_t fde : 1;
134 uint32_t acf : 1;
135 uint32_t tstm : 1;
138 uint32_t rtrle : 1;
140 uint32_t ilbp : 1;
141 uint32_t ena : 1;
[all …]
/qemu/tests/unit/
H A Dtest-x86-topo.c34 * simple tests for 1 thread per core, 1 core per module, in test_topo_bits()
35 * 1 module per die, 1 die per package in test_topo_bits()
37 topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; in test_topo_bits()
43 topo_info = (X86CPUTopoInfo) {1, 1, 1, 1}; in test_topo_bits()
45 g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1), ==, 1); in test_topo_bits()
52 topo_info = (X86CPUTopoInfo) {1, 1, 1, 2}; in test_topo_bits()
53 g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 1); in test_topo_bits()
54 topo_info = (X86CPUTopoInfo) {1, 1, 1, 3}; in test_topo_bits()
56 topo_info = (X86CPUTopoInfo) {1, 1, 1, 4}; in test_topo_bits()
59 topo_info = (X86CPUTopoInfo) {1, 1, 1, 14}; in test_topo_bits()
[all …]
/qemu/target/i386/kvm/
H A Dhyperv-proto.h32 #define HV_VP_RUNTIME_AVAILABLE (1u << 0)
33 #define HV_TIME_REF_COUNT_AVAILABLE (1u << 1)
34 #define HV_SYNIC_AVAILABLE (1u << 2)
35 #define HV_SYNTIMERS_AVAILABLE (1u << 3)
36 #define HV_APIC_ACCESS_AVAILABLE (1u << 4)
37 #define HV_HYPERCALL_AVAILABLE (1u << 5)
38 #define HV_VP_INDEX_AVAILABLE (1u << 6)
39 #define HV_RESET_AVAILABLE (1u << 7)
40 #define HV_REFERENCE_TSC_AVAILABLE (1u << 9)
41 #define HV_ACCESS_FREQUENCY_MSRS (1u << 11)
[all …]
/qemu/target/arm/
H A Dcpregs.h51 ARM_CP_CONST = 1 << 4,
53 ARM_CP_64BIT = 1 << 5,
58 ARM_CP_SUPPRESS_TB_END = 1 << 6,
64 ARM_CP_OVERRIDE = 1 << 7,
71 ARM_CP_ALIAS = 1 << 8,
77 ARM_CP_IO = 1 << 9,
84 ARM_CP_NO_RAW = 1 << 10,
90 ARM_CP_RAISES_EXC = 1 << 11,
96 ARM_CP_NEWEL = 1 << 12,
101 ARM_CP_FPU = 1 << 13,
[all …]
/qemu/target/i386/
H A Dcpu.h48 R_ECX = 1,
65 R_CL = 1,
76 R_CS = 1,
87 #define DESC_G_MASK (1 << DESC_G_SHIFT)
89 #define DESC_B_MASK (1 << DESC_B_SHIFT)
91 #define DESC_L_MASK (1 << DESC_L_SHIFT)
93 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
95 #define DESC_P_MASK (1 << DESC_P_SHIFT)
99 #define DESC_S_MASK (1 << DESC_S_SHIFT)
102 #define DESC_A_MASK (1 << 8)
[all …]

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