Lines Matching full:1

18     FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
20     FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
22     FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
24     FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
26     FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
28     FIELD(CRF_WPROT, ACTIVE, 0, 1)
32     FIELD(APLL_CTRL, CLKOUTDIV, 17, 1)
33     FIELD(APLL_CTRL, DIV2, 16, 1)
35     FIELD(APLL_CTRL, BYPASS, 3, 1)
36     FIELD(APLL_CTRL, RESET, 0, 1)
44     FIELD(APLL_FRAC_CFG, ENABLED, 31, 1)
46     FIELD(APLL_FRAC_CFG, ALGRTHM, 19, 1)
47     FIELD(APLL_FRAC_CFG, ORDER, 18, 1)
52     FIELD(DPLL_CTRL, CLKOUTDIV, 17, 1)
53     FIELD(DPLL_CTRL, DIV2, 16, 1)
55     FIELD(DPLL_CTRL, BYPASS, 3, 1)
56     FIELD(DPLL_CTRL, RESET, 0, 1)
64     FIELD(DPLL_FRAC_CFG, ENABLED, 31, 1)
66     FIELD(DPLL_FRAC_CFG, ALGRTHM, 19, 1)
67     FIELD(DPLL_FRAC_CFG, ORDER, 18, 1)
72     FIELD(VPLL_CTRL, CLKOUTDIV, 17, 1)
73     FIELD(VPLL_CTRL, DIV2, 16, 1)
75     FIELD(VPLL_CTRL, BYPASS, 3, 1)
76     FIELD(VPLL_CTRL, RESET, 0, 1)
84     FIELD(VPLL_FRAC_CFG, ENABLED, 31, 1)
86     FIELD(VPLL_FRAC_CFG, ALGRTHM, 19, 1)
87     FIELD(VPLL_FRAC_CFG, ORDER, 18, 1)
90     FIELD(PLL_STATUS, VPLL_STABLE, 5, 1)
91     FIELD(PLL_STATUS, DPLL_STABLE, 4, 1)
92     FIELD(PLL_STATUS, APLL_STABLE, 3, 1)
93     FIELD(PLL_STATUS, VPLL_LOCK, 2, 1)
94     FIELD(PLL_STATUS, DPLL_LOCK, 1, 1)
95     FIELD(PLL_STATUS, APLL_LOCK, 0, 1)
103     FIELD(ACPU_CTRL, CLKACT_HALF, 25, 1)
104     FIELD(ACPU_CTRL, CLKACT_FULL, 24, 1)
108     FIELD(DBG_TRACE_CTRL, CLKACT, 24, 1)
112     FIELD(DBG_FPD_CTRL, CLKACT, 24, 1)
116     FIELD(DP_VIDEO_REF_CTRL, CLKACT, 24, 1)
121     FIELD(DP_AUDIO_REF_CTRL, CLKACT, 24, 1)
126     FIELD(DP_STC_REF_CTRL, CLKACT, 24, 1)
131     FIELD(DDR_CTRL, CLKACT, 24, 1)
135     FIELD(GPU_REF_CTRL, PP1_CLKACT, 26, 1)
136     FIELD(GPU_REF_CTRL, PP0_CLKACT, 25, 1)
137     FIELD(GPU_REF_CTRL, CLKACT, 24, 1)
141     FIELD(SATA_REF_CTRL, CLKACT, 24, 1)
145     FIELD(PCIE_REF_CTRL, CLKACT, 24, 1)
149     FIELD(GDMA_REF_CTRL, CLKACT, 24, 1)
153     FIELD(DPDMA_REF_CTRL, CLKACT, 24, 1)
157     FIELD(TOPSW_MAIN_CTRL, CLKACT, 24, 1)
161     FIELD(TOPSW_LSBUS_CTRL, CLKACT, 24, 1)
168     FIELD(RST_FPD_TOP, PCIE_CFG_RESET, 19, 1)
169     FIELD(RST_FPD_TOP, PCIE_BRIDGE_RESET, 18, 1)
170     FIELD(RST_FPD_TOP, PCIE_CTRL_RESET, 17, 1)
171     FIELD(RST_FPD_TOP, DP_RESET, 16, 1)
172     FIELD(RST_FPD_TOP, SWDT_RESET, 15, 1)
173     FIELD(RST_FPD_TOP, AFI_FM5_RESET, 12, 1)
174     FIELD(RST_FPD_TOP, AFI_FM4_RESET, 11, 1)
175     FIELD(RST_FPD_TOP, AFI_FM3_RESET, 10, 1)
176     FIELD(RST_FPD_TOP, AFI_FM2_RESET, 9, 1)
177     FIELD(RST_FPD_TOP, AFI_FM1_RESET, 8, 1)
178     FIELD(RST_FPD_TOP, AFI_FM0_RESET, 7, 1)
179     FIELD(RST_FPD_TOP, GDMA_RESET, 6, 1)
180     FIELD(RST_FPD_TOP, GPU_PP1_RESET, 5, 1)
181     FIELD(RST_FPD_TOP, GPU_PP0_RESET, 4, 1)
182     FIELD(RST_FPD_TOP, GPU_RESET, 3, 1)
183     FIELD(RST_FPD_TOP, GT_RESET, 2, 1)
184     FIELD(RST_FPD_TOP, SATA_RESET, 1, 1)
186     FIELD(RST_FPD_APU, ACPU3_PWRON_RESET, 13, 1)
187     FIELD(RST_FPD_APU, ACPU2_PWRON_RESET, 12, 1)
188     FIELD(RST_FPD_APU, ACPU1_PWRON_RESET, 11, 1)
189     FIELD(RST_FPD_APU, ACPU0_PWRON_RESET, 10, 1)
190     FIELD(RST_FPD_APU, APU_L2_RESET, 8, 1)
191     FIELD(RST_FPD_APU, ACPU3_RESET, 3, 1)
192     FIELD(RST_FPD_APU, ACPU2_RESET, 2, 1)
193     FIELD(RST_FPD_APU, ACPU1_RESET, 1, 1)
194     FIELD(RST_FPD_APU, ACPU0_RESET, 0, 1)
196     FIELD(RST_DDR_SS, DDR_RESET, 3, 1)
197     FIELD(RST_DDR_SS, APM_RESET, 2, 1)
199 #define CRF_R_MAX (R_RST_DDR_SS + 1)