Lines Matching full:1
48 R_ECX = 1,
65 R_CL = 1,
76 R_CS = 1,
87 #define DESC_G_MASK (1 << DESC_G_SHIFT)
89 #define DESC_B_MASK (1 << DESC_B_SHIFT)
91 #define DESC_L_MASK (1 << DESC_L_SHIFT)
93 #define DESC_AVL_MASK (1 << DESC_AVL_SHIFT)
95 #define DESC_P_MASK (1 << DESC_P_SHIFT)
99 #define DESC_S_MASK (1 << DESC_S_SHIFT)
102 #define DESC_A_MASK (1 << 8)
104 #define DESC_CS_MASK (1 << 11) /* 1=code segment 0=data segment */
105 #define DESC_C_MASK (1 << 10) /* code: conforming */
106 #define DESC_R_MASK (1 << 9) /* code: readable */
108 #define DESC_E_MASK (1 << 10) /* data: expansion direction */
109 #define DESC_W_MASK (1 << 9) /* data: writable */
111 #define DESC_TSS_BUSY_MASK (1 << 9)
174 #define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
175 #define HF_CS32_MASK (1 << HF_CS32_SHIFT)
176 #define HF_SS32_MASK (1 << HF_SS32_SHIFT)
177 #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
178 #define HF_PE_MASK (1 << HF_PE_SHIFT)
179 #define HF_TF_MASK (1 << HF_TF_SHIFT)
180 #define HF_MP_MASK (1 << HF_MP_SHIFT)
181 #define HF_EM_MASK (1 << HF_EM_SHIFT)
182 #define HF_TS_MASK (1 << HF_TS_SHIFT)
184 #define HF_LMA_MASK (1 << HF_LMA_SHIFT)
185 #define HF_CS64_MASK (1 << HF_CS64_SHIFT)
186 #define HF_RF_MASK (1 << HF_RF_SHIFT)
187 #define HF_VM_MASK (1 << HF_VM_SHIFT)
188 #define HF_AC_MASK (1 << HF_AC_SHIFT)
189 #define HF_SMM_MASK (1 << HF_SMM_SHIFT)
190 #define HF_SVME_MASK (1 << HF_SVME_SHIFT)
191 #define HF_GUEST_MASK (1 << HF_GUEST_SHIFT)
192 #define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
193 #define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
194 #define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
195 #define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
196 #define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
197 #define HF_UMIP_MASK (1 << HF_UMIP_SHIFT)
198 #define HF_AVX_EN_MASK (1 << HF_AVX_EN_SHIFT)
203 #define HF2_HIF_SHIFT 1 /* value of IF_MASK when entering SVM */
212 #define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
213 #define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
214 #define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
215 #define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
216 #define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
217 #define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
218 #define HF2_NPT_MASK (1 << HF2_NPT_SHIFT)
219 #define HF2_IGNNE_MASK (1 << HF2_IGNNE_SHIFT)
220 #define HF2_VGIF_MASK (1 << HF2_VGIF_SHIFT)
223 #define CR0_MP_SHIFT 1
225 #define CR0_PE_MASK (1U << 0)
226 #define CR0_MP_MASK (1U << 1)
227 #define CR0_EM_MASK (1U << 2)
228 #define CR0_TS_MASK (1U << 3)
229 #define CR0_ET_MASK (1U << 4)
230 #define CR0_NE_MASK (1U << 5)
231 #define CR0_WP_MASK (1U << 16)
232 #define CR0_AM_MASK (1U << 18)
233 #define CR0_NW_MASK (1U << 29)
234 #define CR0_CD_MASK (1U << 30)
235 #define CR0_PG_MASK (1U << 31)
237 #define CR4_VME_MASK (1U << 0)
238 #define CR4_PVI_MASK (1U << 1)
239 #define CR4_TSD_MASK (1U << 2)
240 #define CR4_DE_MASK (1U << 3)
241 #define CR4_PSE_MASK (1U << 4)
242 #define CR4_PAE_MASK (1U << 5)
243 #define CR4_MCE_MASK (1U << 6)
244 #define CR4_PGE_MASK (1U << 7)
245 #define CR4_PCE_MASK (1U << 8)
247 #define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
248 #define CR4_OSXMMEXCPT_MASK (1U << 10)
249 #define CR4_UMIP_MASK (1U << 11)
250 #define CR4_LA57_MASK (1U << 12)
251 #define CR4_VMXE_MASK (1U << 13)
252 #define CR4_SMXE_MASK (1U << 14)
253 #define CR4_FSGSBASE_MASK (1U << 16)
254 #define CR4_PCIDE_MASK (1U << 17)
255 #define CR4_OSXSAVE_MASK (1U << 18)
256 #define CR4_SMEP_MASK (1U << 20)
257 #define CR4_SMAP_MASK (1U << 21)
258 #define CR4_PKE_MASK (1U << 22)
259 #define CR4_PKS_MASK (1U << 24)
260 #define CR4_LAM_SUP_MASK (1U << 28)
263 #define CR4_FRED_MASK (1ULL << 32)
278 #define DR6_BD (1 << 13)
279 #define DR6_BS (1 << 14)
280 #define DR6_BT (1 << 15)
283 #define DR7_GD (1 << 13)
298 #define PG_RW_BIT 1
310 #define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
311 #define PG_RW_MASK (1 << PG_RW_BIT)
312 #define PG_USER_MASK (1 << PG_USER_BIT)
313 #define PG_PWT_MASK (1 << PG_PWT_BIT)
314 #define PG_PCD_MASK (1 << PG_PCD_BIT)
315 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
316 #define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
317 #define PG_PSE_MASK (1 << PG_PSE_BIT)
318 #define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
319 #define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
323 #define PG_NX_MASK (1ULL << PG_NX_BIT)
325 #define PG_ERROR_W_BIT 1
328 #define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
334 #define PG_MODE_PAE (1 << 0)
335 #define PG_MODE_LMA (1 << 1)
336 #define PG_MODE_NXE (1 << 2)
337 #define PG_MODE_PSE (1 << 3)
338 #define PG_MODE_LA57 (1 << 4)
342 #define PG_MODE_WP (1 << 16)
343 #define PG_MODE_PKE (1 << 17)
344 #define PG_MODE_PKS (1 << 18)
345 #define PG_MODE_SMEP (1 << 19)
346 #define PG_MODE_PG (1 << 20)
348 #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
349 #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits */
350 #define MCG_LMCE_P (1ULL<<27) /* Local Machine Check Supported */
357 #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
358 #define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
359 #define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
360 #define MCG_STATUS_LMCE (1ULL<<3) /* Local MCE signaled */
362 #define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Local MCE enabled */
364 #define MCI_STATUS_VAL (1ULL<<63) /* valid error */
365 #define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
366 #define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
367 #define MCI_STATUS_EN (1ULL<<60) /* error enabled */
368 #define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
369 #define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
370 #define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
371 #define MCI_STATUS_S (1ULL<<56) /* Signaled machine check */
372 #define MCI_STATUS_AR (1ULL<<55) /* Action required */
373 #define MCI_STATUS_DEFERRED (1ULL<<44) /* Deferred error */
374 #define MCI_STATUS_POISON (1ULL<<43) /* Poisoned data consumed */
378 #define MCM_ADDR_LINEAR 1 /* linear address */
385 #define MSR_IA32_APICBASE_BSP (1<<8)
386 #define MSR_IA32_APICBASE_ENABLE (1<<11)
387 #define MSR_IA32_APICBASE_EXTD (1 << 10)
402 #define ARCH_CAP_TSX_CTRL_MSR (1<<7)
420 #define FEATURE_CONTROL_LOCKED (1<<0)
421 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1ULL << 1)
422 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
423 #define FEATURE_CONTROL_SGX_LC (1ULL << 17)
424 #define FEATURE_CONTROL_SGX (1ULL << 18)
425 #define FEATURE_CONTROL_LMCE (1<<20)
439 #define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
440 #define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
457 #define MSR_IA32_MISC_ENABLE_DEFAULT 1
458 #define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
461 #define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
463 #define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
511 #define MSR_EFER_SCE (1 << 0)
512 #define MSR_EFER_LME (1 << 8)
513 #define MSR_EFER_LMA (1 << 10)
514 #define MSR_EFER_NXE (1 << 11)
515 #define MSR_EFER_SVME (1 << 12)
516 #define MSR_EFER_FFXSR (1 << 14)
544 #define MSR_IA32_FRED_RSP1 0x000001cd /* Stack level 1 regular stack pointer */
548 #define MSR_IA32_FRED_SSP1 0x000001d1 /* Stack level 1 shadow stack pointer in r…
580 #define XSTATE_SSE_BIT 1
593 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
594 #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
595 #define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
596 #define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
597 #define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
598 #define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
599 #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
600 #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
601 #define XSTATE_PT_MASK (1ULL << XSTATE_PT_BIT)
602 #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
603 #define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT)
604 #define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT)
605 #define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT)
609 #define ESA_FEATURE_ALIGN64_BIT 1
612 #define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT)
613 #define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT)
631 FEAT_1_EDX, /* CPUID[1].EDX */
632 FEAT_1_ECX, /* CPUID[1].ECX */
636 FEAT_7_1_EAX, /* CPUID[EAX=7,ECX=1].EAX */
649 FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
668 FEAT_SGX_12_1_EAX, /* CPUID[EAX=0x12,ECX=1].EAX (SGX ATTRIBUTES[31:0]) */
669 FEAT_XSAVE_XSS_LO, /* CPUID[EAX=0xd,ECX=1].ECX */
670 FEAT_XSAVE_XSS_HI, /* CPUID[EAX=0xd,ECX=1].EDX */
671 FEAT_7_1_ECX, /* CPUID[EAX=7,ECX=1].ECX */
672 FEAT_7_1_EDX, /* CPUID[EAX=7,ECX=1].EDX */
691 #define CPUID_FP87 (1U << 0)
692 #define CPUID_VME (1U << 1)
693 #define CPUID_DE (1U << 2)
694 #define CPUID_PSE (1U << 3)
695 #define CPUID_TSC (1U << 4)
696 #define CPUID_MSR (1U << 5)
697 #define CPUID_PAE (1U << 6)
698 #define CPUID_MCE (1U << 7)
699 #define CPUID_CX8 (1U << 8)
700 #define CPUID_APIC (1U << 9)
701 #define CPUID_SEP (1U << 11) /* sysenter/sysexit */
702 #define CPUID_MTRR (1U << 12)
703 #define CPUID_PGE (1U << 13)
704 #define CPUID_MCA (1U << 14)
705 #define CPUID_CMOV (1U << 15)
706 #define CPUID_PAT (1U << 16)
707 #define CPUID_PSE36 (1U << 17)
708 #define CPUID_PN (1U << 18)
709 #define CPUID_CLFLUSH (1U << 19)
710 #define CPUID_DTS (1U << 21)
711 #define CPUID_ACPI (1U << 22)
712 #define CPUID_MMX (1U << 23)
713 #define CPUID_FXSR (1U << 24)
714 #define CPUID_SSE (1U << 25)
715 #define CPUID_SSE2 (1U << 26)
716 #define CPUID_SS (1U << 27)
717 #define CPUID_HT (1U << 28)
718 #define CPUID_TM (1U << 29)
719 #define CPUID_IA64 (1U << 30)
720 #define CPUID_PBE (1U << 31)
722 #define CPUID_EXT_SSE3 (1U << 0)
723 #define CPUID_EXT_PCLMULQDQ (1U << 1)
724 #define CPUID_EXT_DTES64 (1U << 2)
725 #define CPUID_EXT_MONITOR (1U << 3)
726 #define CPUID_EXT_DSCPL (1U << 4)
727 #define CPUID_EXT_VMX (1U << 5)
728 #define CPUID_EXT_SMX (1U << 6)
729 #define CPUID_EXT_EST (1U << 7)
730 #define CPUID_EXT_TM2 (1U << 8)
731 #define CPUID_EXT_SSSE3 (1U << 9)
732 #define CPUID_EXT_CID (1U << 10)
733 #define CPUID_EXT_FMA (1U << 12)
734 #define CPUID_EXT_CX16 (1U << 13)
735 #define CPUID_EXT_XTPR (1U << 14)
736 #define CPUID_EXT_PDCM (1U << 15)
737 #define CPUID_EXT_PCID (1U << 17)
738 #define CPUID_EXT_DCA (1U << 18)
739 #define CPUID_EXT_SSE41 (1U << 19)
740 #define CPUID_EXT_SSE42 (1U << 20)
741 #define CPUID_EXT_X2APIC (1U << 21)
742 #define CPUID_EXT_MOVBE (1U << 22)
743 #define CPUID_EXT_POPCNT (1U << 23)
744 #define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
745 #define CPUID_EXT_AES (1U << 25)
746 #define CPUID_EXT_XSAVE (1U << 26)
747 #define CPUID_EXT_OSXSAVE (1U << 27)
748 #define CPUID_EXT_AVX (1U << 28)
749 #define CPUID_EXT_F16C (1U << 29)
750 #define CPUID_EXT_RDRAND (1U << 30)
751 #define CPUID_EXT_HYPERVISOR (1U << 31)
753 #define CPUID_EXT2_FPU (1U << 0)
754 #define CPUID_EXT2_VME (1U << 1)
755 #define CPUID_EXT2_DE (1U << 2)
756 #define CPUID_EXT2_PSE (1U << 3)
757 #define CPUID_EXT2_TSC (1U << 4)
758 #define CPUID_EXT2_MSR (1U << 5)
759 #define CPUID_EXT2_PAE (1U << 6)
760 #define CPUID_EXT2_MCE (1U << 7)
761 #define CPUID_EXT2_CX8 (1U << 8)
762 #define CPUID_EXT2_APIC (1U << 9)
763 #define CPUID_EXT2_SYSCALL (1U << 11)
764 #define CPUID_EXT2_MTRR (1U << 12)
765 #define CPUID_EXT2_PGE (1U << 13)
766 #define CPUID_EXT2_MCA (1U << 14)
767 #define CPUID_EXT2_CMOV (1U << 15)
768 #define CPUID_EXT2_PAT (1U << 16)
769 #define CPUID_EXT2_PSE36 (1U << 17)
770 #define CPUID_EXT2_MP (1U << 19)
771 #define CPUID_EXT2_NX (1U << 20)
772 #define CPUID_EXT2_MMXEXT (1U << 22)
773 #define CPUID_EXT2_MMX (1U << 23)
774 #define CPUID_EXT2_FXSR (1U << 24)
775 #define CPUID_EXT2_FFXSR (1U << 25)
776 #define CPUID_EXT2_PDPE1GB (1U << 26)
777 #define CPUID_EXT2_RDTSCP (1U << 27)
778 #define CPUID_EXT2_LM (1U << 29)
779 #define CPUID_EXT2_3DNOWEXT (1U << 30)
780 #define CPUID_EXT2_3DNOW (1U << 31)
782 /* CPUID[8000_0001].EDX bits that are aliases of CPUID[1].EDX bits on AMD CPUs */
793 #define CPUID_EXT3_LAHF_LM (1U << 0)
794 #define CPUID_EXT3_CMP_LEG (1U << 1)
795 #define CPUID_EXT3_SVM (1U << 2)
796 #define CPUID_EXT3_EXTAPIC (1U << 3)
797 #define CPUID_EXT3_CR8LEG (1U << 4)
798 #define CPUID_EXT3_ABM (1U << 5)
799 #define CPUID_EXT3_SSE4A (1U << 6)
800 #define CPUID_EXT3_MISALIGNSSE (1U << 7)
801 #define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
802 #define CPUID_EXT3_OSVW (1U << 9)
803 #define CPUID_EXT3_IBS (1U << 10)
804 #define CPUID_EXT3_XOP (1U << 11)
805 #define CPUID_EXT3_SKINIT (1U << 12)
806 #define CPUID_EXT3_WDT (1U << 13)
807 #define CPUID_EXT3_LWP (1U << 15)
808 #define CPUID_EXT3_FMA4 (1U << 16)
809 #define CPUID_EXT3_TCE (1U << 17)
810 #define CPUID_EXT3_NODEID (1U << 19)
811 #define CPUID_EXT3_TBM (1U << 21)
812 #define CPUID_EXT3_TOPOEXT (1U << 22)
813 #define CPUID_EXT3_PERFCORE (1U << 23)
814 #define CPUID_EXT3_PERFNB (1U << 24)
816 #define CPUID_SVM_NPT (1U << 0)
817 #define CPUID_SVM_LBRV (1U << 1)
818 #define CPUID_SVM_SVMLOCK (1U << 2)
819 #define CPUID_SVM_NRIPSAVE (1U << 3)
820 #define CPUID_SVM_TSCSCALE (1U << 4)
821 #define CPUID_SVM_VMCBCLEAN (1U << 5)
822 #define CPUID_SVM_FLUSHASID (1U << 6)
823 #define CPUID_SVM_DECODEASSIST (1U << 7)
824 #define CPUID_SVM_PAUSEFILTER (1U << 10)
825 #define CPUID_SVM_PFTHRESHOLD (1U << 12)
826 #define CPUID_SVM_AVIC (1U << 13)
827 #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)
828 #define CPUID_SVM_VGIF (1U << 16)
829 #define CPUID_SVM_VNMI (1U << 25)
830 #define CPUID_SVM_SVME_ADDR_CHK (1U << 28)
833 #define CPUID_7_0_EBX_FSGSBASE (1U << 0)
835 #define CPUID_7_0_EBX_TSC_ADJUST (1U << 1)
837 #define CPUID_7_0_EBX_SGX (1U << 2)
838 /* 1st Group of Advanced Bit Manipulation Extensions */
839 #define CPUID_7_0_EBX_BMI1 (1U << 3)
841 #define CPUID_7_0_EBX_HLE (1U << 4)
843 #define CPUID_7_0_EBX_AVX2 (1U << 5)
845 #define CPUID_7_0_EBX_FDP_EXCPTN_ONLY (1u << 6)
847 #define CPUID_7_0_EBX_SMEP (1U << 7)
849 #define CPUID_7_0_EBX_BMI2 (1U << 8)
851 #define CPUID_7_0_EBX_ERMS (1U << 9)
853 #define CPUID_7_0_EBX_INVPCID (1U << 10)
855 #define CPUID_7_0_EBX_RTM (1U << 11)
857 #define CPUID_7_0_EBX_ZERO_FCS_FDS (1U << 13)
859 #define CPUID_7_0_EBX_MPX (1U << 14)
861 #define CPUID_7_0_EBX_AVX512F (1U << 16)
863 #define CPUID_7_0_EBX_AVX512DQ (1U << 17)
865 #define CPUID_7_0_EBX_RDSEED (1U << 18)
867 #define CPUID_7_0_EBX_ADX (1U << 19)
869 #define CPUID_7_0_EBX_SMAP (1U << 20)
871 #define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
873 #define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
875 #define CPUID_7_0_EBX_CLWB (1U << 24)
877 #define CPUID_7_0_EBX_INTEL_PT (1U << 25)
879 #define CPUID_7_0_EBX_AVX512PF (1U << 26)
881 #define CPUID_7_0_EBX_AVX512ER (1U << 27)
883 #define CPUID_7_0_EBX_AVX512CD (1U << 28)
885 #define CPUID_7_0_EBX_SHA_NI (1U << 29)
887 #define CPUID_7_0_EBX_AVX512BW (1U << 30)
889 #define CPUID_7_0_EBX_AVX512VL (1U << 31)
892 #define CPUID_7_0_ECX_AVX512_VBMI (1U << 1)
894 #define CPUID_7_0_ECX_UMIP (1U << 2)
896 #define CPUID_7_0_ECX_PKU (1U << 3)
898 #define CPUID_7_0_ECX_OSPKE (1U << 4)
900 #define CPUID_7_0_ECX_WAITPKG (1U << 5)
902 #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6)
904 #define CPUID_7_0_ECX_GFNI (1U << 8)
906 #define CPUID_7_0_ECX_VAES (1U << 9)
908 #define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
910 #define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
912 #define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
914 #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14)
916 #define CPUID_7_0_ECX_LA57 (1U << 16)
918 #define CPUID_7_0_ECX_RDPID (1U << 22)
920 #define CPUID_7_0_ECX_KeyLocker (1U << 23)
922 #define CPUID_7_0_ECX_BUS_LOCK_DETECT (1U << 24)
924 #define CPUID_7_0_ECX_CLDEMOTE (1U << 25)
926 #define CPUID_7_0_ECX_MOVDIRI (1U << 27)
928 #define CPUID_7_0_ECX_MOVDIR64B (1U << 28)
930 #define CPUID_7_0_ECX_SGX_LC (1U << 30)
932 #define CPUID_7_0_ECX_PKS (1U << 31)
935 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
937 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
939 #define CPUID_7_0_EDX_FSRM (1U << 4)
941 #define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8)
943 #define CPUID_7_0_EDX_MD_CLEAR (1U << 10)
945 #define CPUID_7_0_EDX_SERIALIZE (1U << 14)
947 #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
949 #define CPUID_7_0_EDX_ARCH_LBR (1U << 19)
951 #define CPUID_7_0_EDX_AMX_BF16 (1U << 22)
953 #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
955 #define CPUID_7_0_EDX_AMX_TILE (1U << 24)
957 #define CPUID_7_0_EDX_AMX_INT8 (1U << 25)
959 #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
961 #define CPUID_7_0_EDX_STIBP (1U << 27)
963 #define CPUID_7_0_EDX_FLUSH_L1D (1U << 28)
965 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)
967 #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30)
969 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31)
972 #define CPUID_7_1_EAX_SHA512 (1U << 0)
974 #define CPUID_7_1_EAX_SM3 (1U << 1)
976 #define CPUID_7_1_EAX_SM4 (1U << 2)
978 #define CPUID_7_1_EAX_AVX_VNNI (1U << 4)
980 #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5)
982 #define CPUID_7_1_EAX_LASS (1U << 6)
984 #define CPUID_7_1_EAX_CMPCCXADD (1U << 7)
986 #define CPUID_7_1_EAX_FZRM (1U << 10)
988 #define CPUID_7_1_EAX_FSRS (1U << 11)
990 #define CPUID_7_1_EAX_FSRC (1U << 12)
992 #define CPUID_7_1_EAX_FRED (1U << 17)
994 #define CPUID_7_1_EAX_LKGS (1U << 18)
996 #define CPUID_7_1_EAX_WRMSRNS (1U << 19)
998 #define CPUID_7_1_EAX_AMX_FP16 (1U << 21)
1000 #define CPUID_7_1_EAX_AVX_IFMA (1U << 23)
1002 #define CPUID_7_1_EAX_LAM (1U << 26)
1005 #define CPUID_7_1_ECX_MSR_IMM (1U << 5)
1008 #define CPUID_7_1_EDX_AVX_VNNI_INT8 (1U << 4)
1010 #define CPUID_7_1_EDX_AVX_NE_CONVERT (1U << 5)
1012 #define CPUID_7_1_EDX_AMX_COMPLEX (1U << 8)
1014 #define CPUID_7_1_EDX_AVX_VNNI_INT16 (1U << 10)
1015 /* PREFETCHIT0/1 Instructions */
1016 #define CPUID_7_1_EDX_PREFETCHITI (1U << 14)
1018 #define CPUID_7_1_EDX_AVX10 (1U << 19)
1021 #define CPUID_7_2_EDX_PSFD (1U << 0)
1023 #define CPUID_7_2_EDX_IPRED_CTRL (1U << 1)
1025 #define CPUID_7_2_EDX_RRSBA_CTRL (1U << 2)
1027 #define CPUID_7_2_EDX_DDPD_U (1U << 3)
1029 #define CPUID_7_2_EDX_BHI_CTRL (1U << 4)
1032 #define CPUID_7_2_EDX_MCDT_NO (1U << 5)
1035 #define CPUID_D_1_EAX_XFD (1U << 4)
1038 #define CPUID_14_0_ECX_LIP (1U << 31)
1041 #define CPUID_24_0_EBX_AVX10_128 (1U << 16)
1043 #define CPUID_24_0_EBX_AVX10_256 (1U << 17)
1045 #define CPUID_24_0_EBX_AVX10_512 (1U << 18)
1052 #define CPUID_8000_0007_EBX_OVERFLOW_RECOV (1U << 0)
1053 #define CPUID_8000_0007_EBX_SUCCOR (1U << 1)
1056 #define CPUID_KVM_CLOCK (1U << KVM_FEATURE_CLOCKSOURCE)
1058 #define CPUID_KVM_CLOCK2 (1U << KVM_FEATURE_CLOCKSOURCE2)
1060 #define CPUID_KVM_ASYNCPF (1U << KVM_FEATURE_ASYNC_PF)
1062 #define CPUID_KVM_STEAL_TIME (1U << KVM_FEATURE_STEAL_TIME)
1064 #define CPUID_KVM_PV_EOI (1U << KVM_FEATURE_PV_EOI)
1066 #define CPUID_KVM_PV_UNHALT (1U << KVM_FEATURE_PV_UNHALT)
1068 #define CPUID_KVM_POLL_CONTROL (1U << KVM_FEATURE_POLL_CONTROL)
1070 #define CPUID_KVM_ASYNCPF_INT (1U << KVM_FEATURE_ASYNC_PF_INT)
1072 #define CPUID_KVM_MSI_EXT_DEST_ID (1U << KVM_FEATURE_MSI_EXT_DEST_ID)
1075 #define CPUID_KVM_HINTS_REALTIME (1U << KVM_HINTS_REALTIME)
1078 #define CPUID_8000_0008_EBX_CLZERO (1U << 0)
1080 #define CPUID_8000_0008_EBX_XSAVEERPTR (1U << 2)
1082 #define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
1084 #define CPUID_8000_0008_EBX_IBPB (1U << 12)
1086 #define CPUID_8000_0008_EBX_IBRS (1U << 14)
1088 #define CPUID_8000_0008_EBX_STIBP (1U << 15)
1090 #define CPUID_8000_0008_EBX_STIBP_ALWAYS_ON (1U << 17)
1092 #define CPUID_8000_0008_EBX_AMD_SSBD (1U << 24)
1094 #define CPUID_8000_0008_EBX_VIRT_SSBD (1U << 25)
1096 #define CPUID_8000_0008_EBX_AMD_PSFD (1U << 28)
1099 #define CPUID_8000_0021_EAX_NO_NESTED_DATA_BP (1U << 0)
1101 #define CPUID_8000_0021_EAX_FS_GS_BASE_NS (1U << 1)
1103 #define CPUID_8000_0021_EAX_LFENCE_ALWAYS_SERIALIZING (1U << 2)
1105 #define CPUID_8000_0021_EAX_NULL_SEL_CLR_BASE (1U << 6)
1107 #define CPUID_8000_0021_EAX_AUTO_IBRS (1U << 8)
1109 #define CPUID_8000_0021_EAX_PREFETCHI (1U << 20)
1111 #define CPUID_8000_0021_EAX_ERAPS (1U << 24)
1113 #define CPUID_8000_0021_EAX_SBPB (1U << 27)
1115 #define CPUID_8000_0021_EAX_IBPB_BRTYPE (1U << 28)
1117 #define CPUID_8000_0021_EAX_SRSO_NO (1U << 29)
1119 #define CPUID_8000_0021_EAX_SRSO_USER_KERNEL_NO (1U << 30)
1128 #define CPUID_8000_0022_EAX_PERFMON_V2 (1U << 0)
1130 #define CPUID_XSAVE_XSAVEOPT (1U << 0)
1131 #define CPUID_XSAVE_XSAVEC (1U << 1)
1132 #define CPUID_XSAVE_XGETBV1 (1U << 2)
1133 #define CPUID_XSAVE_XSAVES (1U << 3)
1134 #define CPUID_XSAVE_XFD (1U << 4)
1136 #define CPUID_6_EAX_ARAT (1U << 2)
1139 #define CPUID_APM_INVTSC (1U << 8)
1142 #define CPUID_C000_0001_EDX_XSTORE (1U << 2)
1144 #define CPUID_C000_0001_EDX_XSTORE_EN (1U << 3)
1146 #define CPUID_C000_0001_EDX_XCRYPT (1U << 6)
1148 #define CPUID_C000_0001_EDX_XCRYPT_EN (1U << 7)
1150 #define CPUID_C000_0001_EDX_ACE2 (1U << 8)
1152 #define CPUID_C000_0001_EDX_ACE2_EN (1U << 9)
1154 #define CPUID_C000_0001_EDX_PHE (1U << 10)
1156 #define CPUID_C000_0001_EDX_PHE_EN (1U << 11)
1158 #define CPUID_C000_0001_EDX_PMM (1U << 12)
1160 #define CPUID_C000_0001_EDX_PMM_EN (1U << 13)
1203 #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
1204 #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
1208 #define CPUID_B_ECX_TOPO_LEVEL_SMT 1
1219 #define MSR_ARCH_CAP_RDCL_NO (1U << 0)
1220 #define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
1221 #define MSR_ARCH_CAP_RSBA (1U << 2)
1222 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
1223 #define MSR_ARCH_CAP_SSB_NO (1U << 4)
1224 #define MSR_ARCH_CAP_MDS_NO (1U << 5)
1225 #define MSR_ARCH_CAP_PSCHANGE_MC_NO (1U << 6)
1226 #define MSR_ARCH_CAP_TSX_CTRL_MSR (1U << 7)
1227 #define MSR_ARCH_CAP_TAA_NO (1U << 8)
1228 #define MSR_ARCH_CAP_SBDR_SSDP_NO (1U << 13)
1229 #define MSR_ARCH_CAP_FBSDP_NO (1U << 14)
1230 #define MSR_ARCH_CAP_PSDP_NO (1U << 15)
1231 #define MSR_ARCH_CAP_FB_CLEAR (1U << 17)
1232 #define MSR_ARCH_CAP_BHI_NO (1U << 20)
1233 #define MSR_ARCH_CAP_PBRSB_NO (1U << 24)
1234 #define MSR_ARCH_CAP_GDS_NO (1U << 26)
1235 #define MSR_ARCH_CAP_RFDS_NO (1U << 27)
1237 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
1243 #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49)
1244 #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54)
1245 #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55)
1246 #define MSR_VMX_BASIC_ANY_ERRCODE (1ULL << 56)
1247 #define MSR_VMX_BASIC_NESTED_EXCEPTION (1ULL << 58)
1250 #define MSR_VMX_MISC_STORE_LMA (1ULL << 5)
1251 #define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6)
1252 #define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7)
1253 #define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8)
1255 #define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29)
1256 #define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30)
1258 #define MSR_VMX_EPT_EXECONLY (1ULL << 0)
1259 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6)
1260 #define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7)
1261 #define MSR_VMX_EPT_UC (1ULL << 8)
1262 #define MSR_VMX_EPT_WB (1ULL << 14)
1263 #define MSR_VMX_EPT_2MB (1ULL << 16)
1264 #define MSR_VMX_EPT_1GB (1ULL << 17)
1265 #define MSR_VMX_EPT_INVEPT (1ULL << 20)
1266 #define MSR_VMX_EPT_AD_BITS (1ULL << 21)
1267 #define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22)
1268 #define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25)
1269 #define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26)
1270 #define MSR_VMX_EPT_INVVPID (1ULL << 32)
1271 #define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40)
1272 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41)
1273 #define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42)
1274 #define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
1276 #define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
1359 #define HYPERV_FEAT_VAPIC 1
1385 #define EXCP01_DB 1
1430 CC_OP_ADCX = 1, /* CC_DST = C, CC_SRC = rest. */
1572 #define BNDCFG_ENABLE 1ULL
1585 #define ZMM_Y(n) _y_ZMMReg[1 - (n)]
1587 #define XMM_Q(n) _q_XMMReg[1 - (n)]
1590 #define YMM_X(n) _x_YMMReg[1 - (n)]
1594 #define MMX_L(n) _l_MMXReg[1 - (n)]
1595 #define MMX_S(n) _s_MMXReg[1 - (n)]
1765 #define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1)
1809 * CPUID[4].EDX[bit 1], CPUID[0x8000001D].EDX[bit 1].
1847 int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
1877 uint8_t fptags[8]; /* 0 = valid, 1 = empty */
2596 #define MMU_KSMAP32_IDX 1
2614 return (mmu_index & ~1) == MMU_KSMAP64_IDX; in is_mmu_index_smap()
2619 return (mmu_index & ~1) == MMU_USER64_IDX; in is_mmu_index_user()
2625 return mmu_index & 1; in is_mmu_index_32()
2641 #define MCE_INJECT_BROADCAST 1
2667 return -1; in x86_get_a20_mask()
2755 #define CPU_VERSION_LATEST -1
2864 * 1 in (x+y)^x^y, resulting in majority(NOT (x+y), x, y)