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/qemu/tests/qtest/
H A Dfuzz-sb16-test.c21 qtest_outw(s, 0x22c, 0x41); in test_fuzz_sb16_0x1c()
22 qtest_outb(s, 0x22c, 0x00); in test_fuzz_sb16_0x1c()
23 qtest_outw(s, 0x22c, 0x1004); in test_fuzz_sb16_0x1c()
24 qtest_outw(s, 0x22c, 0x001c); in test_fuzz_sb16_0x1c()
33 qtest_outw(s, 0x22c, 0xf141); in test_fuzz_sb16_0x91()
34 qtest_outb(s, 0x22c, 0x00); in test_fuzz_sb16_0x91()
35 qtest_outb(s, 0x22c, 0x24); in test_fuzz_sb16_0x91()
36 qtest_outb(s, 0x22c, 0x91); in test_fuzz_sb16_0x91()
42 * through command 0xd4
49 qtest_outb(s, 0x22c, 0x41); in test_fuzz_sb16_0xd4()
[all …]
H A Dadm1266-test.c21 #define TEST_ADDR (0x12)
23 #define ADM1266_BLACKBOX_CONFIG 0xD3
24 #define ADM1266_PDIO_CONFIG 0xD4
25 #define ADM1266_READ_STATE 0xD9
26 #define ADM1266_READ_BLACKBOX 0xDE
27 #define ADM1266_SET_RTC 0xDF
28 #define ADM1266_GPIO_SYNC_CONFIGURATION 0xE1
29 #define ADM1266_BLACKBOX_INFORMATION 0xE6
30 #define ADM1266_PDIO_STATUS 0xE9
31 #define ADM1266_GPIO_STATUS 0xEA
[all …]
H A Dmax34451-test.c19 #define TEST_ADDR (0x4e)
21 #define MAX34451_MFR_MODE 0xD1
22 #define MAX34451_MFR_VOUT_PEAK 0xD4
23 #define MAX34451_MFR_IOUT_PEAK 0xD5
24 #define MAX34451_MFR_TEMPERATURE_PEAK 0xD6
25 #define MAX34451_MFR_VOUT_MIN 0xD7
27 #define DEFAULT_VOUT 0
28 #define DEFAULT_UV_LIMIT 0
30 #define DEFAULT_SCALE 0x7FFF
31 #define DEFAULT_OV_LIMIT 0x7FFF
[all …]
H A Dadm1272-test.c20 #define TEST_ADDR (0x10)
22 #define ADM1272_RESTART_TIME 0xCC
23 #define ADM1272_MFR_PEAK_IOUT 0xD0
24 #define ADM1272_MFR_PEAK_VIN 0xD1
25 #define ADM1272_MFR_PEAK_VOUT 0xD2
26 #define ADM1272_MFR_PMON_CONTROL 0xD3
27 #define ADM1272_MFR_PMON_CONFIG 0xD4
28 #define ADM1272_MFR_ALERT1_CONFIG 0xD5
29 #define ADM1272_MFR_ALERT2_CONFIG 0xD6
30 #define ADM1272_MFR_PEAK_TEMPERATURE 0xD7
[all …]
/qemu/tests/unit/
H A Dtest-crypto-xts.c46 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
47 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
48 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
49 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
50 0,
52 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
53 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
54 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
55 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 },
56 { 0x91, 0x7c, 0xf6, 0x9e, 0xbd, 0x68, 0xb2, 0xec,
[all …]
H A Dtest-crypto-akcipher.c29 0x30, 0x82, 0x02, 0x5c, 0x02, 0x01, 0x00, 0x02,
30 0x81, 0x81, 0x00, 0xe6, 0x4d, 0x76, 0x4f, 0xb2,
31 0x97, 0x09, 0xad, 0x9d, 0x17, 0x33, 0xf2, 0x30,
32 0x42, 0x83, 0xa9, 0xcb, 0x49, 0xa4, 0x2e, 0x59,
33 0x5e, 0x75, 0x51, 0xd1, 0xac, 0xc8, 0x86, 0x3e,
34 0xdb, 0x72, 0x2e, 0xb2, 0xf7, 0xc3, 0x5b, 0xc7,
35 0xea, 0xed, 0x30, 0xd1, 0xf7, 0x37, 0xee, 0x9d,
36 0x36, 0x59, 0x6f, 0xf8, 0xce, 0xc0, 0x5c, 0x82,
37 0x80, 0x37, 0x83, 0xd7, 0x45, 0x6a, 0xe9, 0xea,
38 0xc5, 0x3a, 0x59, 0x6b, 0x34, 0x31, 0x44, 0x00,
[all …]
H A Dtest-crypto-der.c27 "\x30\x82\x01\x39" /* SEQUENCE, offset: 0, length: 313 */
60 "\x30\x82\x04\xa6" /* SEQUENCE, offset: 0, length 1190 */
72 "\x7f\x30\x25\x03\xd4\x3a\xff\xa2\xe8\xd6\xb5\x1f\x4f\x36\x64\x61"
116 "\x5e\x98\x65\x66\x2f\x3a\xde\xd8\xd4\xee\x6f\x82\xe6\x36\x49\x12"
151 "\x30\x53" /* SEQUENCE, offset 0, length 83 */
164 "\x30\x77" /* SEQUENCE, offset 0, length 119 */
169 "\xa0\x0a" /* CONTEXT SPECIFIC 0, offset 39, length 10 */
177 "\x3a\x6b\x5b\xbc\x0d\x33\xba\xbb\xd4\xa3\xff\x4f\x9e\xdd\xf5\x59"
186 return qcrypto_der_decode_ctx_tag(data, dlen, 0, cb, opaque, errp); in qcrypto_wrapped_decode_ctx_tag0()
228 return 0; in checker_callback()
[all …]
H A Dtest-crypto-ivgen.c40 .sector = 0x1,
49 .sector = 0x1f2e3d4cULL,
58 .sector = 0x1f2e3d4c5b6a7988ULL,
67 .sector = 0x1,
76 .sector = 0x1f2e3d4cULL,
85 .sector = 0x1f2e3d4c5b6a7988ULL,
94 .sector = 0x1,
101 .iv = (const uint8_t *)"\xd4\x83\x71\xb2\xa1\x94\x53\x88"
108 .sector = 0x1f2e3d4cULL,
122 .sector = 0x1f2e3d4c5b6a7988ULL,
[all …]
H A Dtest-crypto-afsplit.c59 "\x83\xd4\xcd\x8e\x89\x1b\xc7\xc5"
110 return '0' + i; in hex()
121 for (i = 0; i < len; i++) { in hex_string()
122 hexstr[i * 2] = hex((bytes[i] >> 4) & 0xf); in hex_string()
123 hexstr[i * 2 + 1] = hex(bytes[i] & 0xf); in hex_string()
125 hexstr[len * 2] = '\0'; in hex_string()
159 memset(key, 0, data->blocklen); in test_afsplit()
185 g_assert(qcrypto_init(NULL) == 0); in main()
187 for (i = 0; i < G_N_ELEMENTS(test_data); i++) { in main()
H A Dtest-crypto-pbkdf.c133 .out = "\x9c\xca\xd6\xd4\x68\x77\x0c\xd5"
221 .key = "pass\0word",
223 .salt = "sa\0lt",
237 .nkey = 0,
344 #if 0
367 return '0' + i; in hex()
378 for (i = 0; i < len; i++) { in hex_string()
379 hexstr[i * 2] = hex((bytes[i] >> 4) & 0xf); in hex_string()
380 hexstr[i * 2 + 1] = hex(bytes[i] & 0xf); in hex_string()
382 hexstr[len * 2] = '\0'; in hex_string()
[all …]
/qemu/tests/bench/
H A Dtest_akcipher_keys.c.inc12 0x30, 0x82, 0x02, 0x5c, 0x02, 0x01, 0x00, 0x02,
13 0x81, 0x81, 0x00, 0xe6, 0x4d, 0x76, 0x4f, 0xb2,
14 0x97, 0x09, 0xad, 0x9d, 0x17, 0x33, 0xf2, 0x30,
15 0x42, 0x83, 0xa9, 0xcb, 0x49, 0xa4, 0x2e, 0x59,
16 0x5e, 0x75, 0x51, 0xd1, 0xac, 0xc8, 0x86, 0x3e,
17 0xdb, 0x72, 0x2e, 0xb2, 0xf7, 0xc3, 0x5b, 0xc7,
18 0xea, 0xed, 0x30, 0xd1, 0xf7, 0x37, 0xee, 0x9d,
19 0x36, 0x59, 0x6f, 0xf8, 0xce, 0xc0, 0x5c, 0x82,
20 0x80, 0x37, 0x83, 0xd7, 0x45, 0x6a, 0xe9, 0xea,
21 0xc5, 0x3a, 0x59, 0x6b, 0x34, 0x31, 0x44, 0x00,
[all …]
/qemu/hw/audio/
H A Dpl041.hx14 REGISTER( rxcr1, 0x00 )
15 REGISTER( txcr1, 0x04 )
16 REGISTER( sr1, 0x08 )
17 REGISTER( isr1, 0x0C )
18 REGISTER( ie1, 0x10 )
19 REGISTER( rxcr2, 0x14 )
20 REGISTER( txcr2, 0x18 )
21 REGISTER( sr2, 0x1C )
22 REGISTER( isr2, 0x20 )
23 REGISTER( ie2, 0x24 )
[all …]
/qemu/hw/uefi/
H A Dvar-service-guid.c15 .data = UUID_LE(0x8be4df61, 0x93ca, 0x11d2, 0xaa, 0x0d,
16 0x00, 0xe0, 0x98, 0x03, 0x2b, 0x8c)
20 .data = UUID_LE(0xd719b2cb, 0x3d3a, 0x4596, 0xa3, 0xbc,
21 0xda, 0xd0, 0x0e, 0x67, 0x65, 0x6f)
25 .data = UUID_LE(0xc076ec0c, 0x7028, 0x4399, 0xa0, 0x72,
26 0x71, 0xee, 0x5c, 0x44, 0x8b, 0x9f)
30 .data = UUID_LE(0xf0a30bc7, 0xaf08, 0x4556, 0x99, 0xc4,
31 0x0, 0x10, 0x9, 0xc9, 0x3a, 0x44)
37 .data = UUID_LE(0xc1c41626, 0x504c, 0x4092, 0xac, 0xa9,
38 0x41, 0xf9, 0x36, 0x93, 0x43, 0x28)
[all …]
/qemu/crypto/
H A Dsm4.c16 0xd6, 0x90, 0xe9, 0xfe, 0xcc, 0xe1, 0x3d, 0xb7,
17 0x16, 0xb6, 0x14, 0xc2, 0x28, 0xfb, 0x2c, 0x05,
18 0x2b, 0x67, 0x9a, 0x76, 0x2a, 0xbe, 0x04, 0xc3,
19 0xaa, 0x44, 0x13, 0x26, 0x49, 0x86, 0x06, 0x99,
20 0x9c, 0x42, 0x50, 0xf4, 0x91, 0xef, 0x98, 0x7a,
21 0x33, 0x54, 0x0b, 0x43, 0xed, 0xcf, 0xac, 0x62,
22 0xe4, 0xb3, 0x1c, 0xa9, 0xc9, 0x08, 0xe8, 0x95,
23 0x80, 0xdf, 0x94, 0xfa, 0x75, 0x8f, 0x3f, 0xa6,
24 0x47, 0x07, 0xa7, 0xfc, 0xf3, 0x73, 0x17, 0xba,
25 0x83, 0x59, 0x3c, 0x19, 0xe6, 0x85, 0x4f, 0xa8,
[all …]
/qemu/hw/ide/
H A Dide-internal.h16 #define ATA_DEV_SELECT 0x10
20 #define ATA_DEV_ALWAYS_ON 0xA0
21 #define ATA_DEV_LBA 0x40
22 #define ATA_DEV_LBA_MSB 0x0F /* LBA 24:27 */
23 #define ATA_DEV_HS 0x0F /* HS 3:0 */
27 #define ERR_STAT 0x01
28 #define INDEX_STAT 0x02
29 #define ECC_STAT 0x04 /* Corrected error */
30 #define DRQ_STAT 0x08
31 #define SEEK_STAT 0x10
[all …]
/qemu/hw/sensor/
H A Dadm1266.c24 #define ADM1266_BLACKBOX_CONFIG 0xD3
25 #define ADM1266_PDIO_CONFIG 0xD4
26 #define ADM1266_READ_STATE 0xD9
27 #define ADM1266_READ_BLACKBOX 0xDE
28 #define ADM1266_SET_RTC 0xDF
29 #define ADM1266_GPIO_SYNC_CONFIGURATION 0xE1
30 #define ADM1266_BLACKBOX_INFORMATION 0xE6
31 #define ADM1266_PDIO_STATUS 0xE9
32 #define ADM1266_GPIO_STATUS 0xEA
35 #define ADM1266_OPERATION_DEFAULT 0x80
[all …]
H A Dadm1272.c22 #define ADM1272_RESTART_TIME 0xCC
23 #define ADM1272_MFR_PEAK_IOUT 0xD0
24 #define ADM1272_MFR_PEAK_VIN 0xD1
25 #define ADM1272_MFR_PEAK_VOUT 0xD2
26 #define ADM1272_MFR_PMON_CONTROL 0xD3
27 #define ADM1272_MFR_PMON_CONFIG 0xD4
28 #define ADM1272_MFR_ALERT1_CONFIG 0xD5
29 #define ADM1272_MFR_ALERT2_CONFIG 0xD6
30 #define ADM1272_MFR_PEAK_TEMPERATURE 0xD7
31 #define ADM1272_MFR_DEVICE_CONFIG 0xD8
[all …]
/qemu/docs/about/
H A Demulation.rst300 $ du sha1.0.bb
301 23128 sha1.0.bb
315 cpu 0 insns: 46765
347 0x40069c, 'bl #0x4002b0', 10 hits, 1093 match hits, Δ+1257 since last match, 98 avg insns/match
348 0x4006ac, 'bl #0x403690', 10 hits, 1094 match hits, Δ+47 since last match, 98 avg insns/match
349 0x4037fc, 'bl #0x4002b0', 18 hits, 1095 match hits, Δ+22 since last match, 98 avg insns/match
350 0x400720, 'bl #0x403690', 10 hits, 1096 match hits, Δ+58 since last match, 98 avg insns/match
351 0x4037fc, 'bl #0x4002b0', 19 hits, 1097 match hits, Δ+22 since last match, 98 avg insns/match
352 0x400730, 'bl #0x403690', 10 hits, 1098 match hits, Δ+33 since last match, 98 avg insns/match
353 0x4037ac, 'bl #0x4002b0', 12 hits, 1099 match hits, Δ+20 since last match, 98 avg insns/match
[all …]
/qemu/include/hw/s390x/
H A Debcdic.h17 0x00, 0x01, 0x02, 0x03, 0x07, 0x09, 0x07, 0x7F,
18 0x07, 0x07, 0x07, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
19 0x10, 0x11, 0x12, 0x13, 0x07, 0x0A, 0x08, 0x07,
20 0x18, 0x19, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
21 0x07, 0x07, 0x1C, 0x07, 0x07, 0x0A, 0x17, 0x1B,
22 0x07, 0x07, 0x07, 0x07, 0x07, 0x05, 0x06, 0x07,
23 0x07, 0x07, 0x16, 0x07, 0x07, 0x07, 0x07, 0x04,
24 0x07, 0x07, 0x07, 0x07, 0x14, 0x15, 0x07, 0x1A,
25 0x20, 0xFF, 0x83, 0x84, 0x85, 0xA0, 0x07, 0x86,
26 0x87, 0xA4, 0x5B, 0x2E, 0x3C, 0x28, 0x2B, 0x21,
[all …]
/qemu/tests/tcg/multiarch/
H A Dtest-aes-main.c.inc42 { { { 0x19, 0x3d, 0xe3, 0xbe, /* start */
43 0xa0, 0xf4, 0xe2, 0x2b,
44 0x9a, 0xc6, 0x8d, 0x2a,
45 0xe9, 0xf8, 0x48, 0x08, } },
47 { { 0xd4, 0xbf, 0x5d, 0x30, /* after shiftrows */
48 0xe0, 0xb4, 0x52, 0xae,
49 0xb8, 0x41, 0x11, 0xf1,
50 0x1e, 0x27, 0x98, 0xe5, } },
52 { { 0x04, 0x66, 0x81, 0xe5, /* after mixcolumns */
53 0xe0, 0xcb, 0x19, 0x9a,
[all …]
/qemu/hw/misc/
H A Daspeed_i3c.c21 REG32(I3C1_REG0, 0x10)
22 REG32(I3C1_REG1, 0x14)
23 FIELD(I3C1_REG1, I2C_MODE, 0, 1)
25 REG32(I3C2_REG0, 0x20)
26 REG32(I3C2_REG1, 0x24)
27 FIELD(I3C2_REG1, I2C_MODE, 0, 1)
29 REG32(I3C3_REG0, 0x30)
30 REG32(I3C3_REG1, 0x34)
31 FIELD(I3C3_REG1, I2C_MODE, 0, 1)
33 REG32(I3C4_REG0, 0x40)
[all …]
/qemu/hw/ppc/
H A Dpnv_sbe.c39 * Reg 0 - 3 : Host to send command packets to SBE
42 #define PSU_HOST_SBE_MBOX_REG0 0x00000000
43 #define PSU_HOST_SBE_MBOX_REG1 0x00000001
44 #define PSU_HOST_SBE_MBOX_REG2 0x00000002
45 #define PSU_HOST_SBE_MBOX_REG3 0x00000003
46 #define PSU_HOST_SBE_MBOX_REG4 0x00000004
47 #define PSU_HOST_SBE_MBOX_REG5 0x00000005
48 #define PSU_HOST_SBE_MBOX_REG6 0x00000006
49 #define PSU_HOST_SBE_MBOX_REG7 0x00000007
50 #define PSU_SBE_DOORBELL_REG_RW 0x00000010
[all …]
/qemu/hw/input/
H A Dps2.c40 #define KBD_CMD_SET_LEDS 0xED /* Set keyboard leds */
41 #define KBD_CMD_ECHO 0xEE
42 #define KBD_CMD_SCANCODE 0xF0 /* Get/set scancode set */
43 #define KBD_CMD_GET_ID 0xF2 /* get keyboard ID */
44 #define KBD_CMD_SET_RATE 0xF3 /* Set typematic rate */
45 #define KBD_CMD_ENABLE 0xF4 /* Enable scanning */
46 #define KBD_CMD_RESET_DISABLE 0xF5 /* reset and disable scanning */
47 #define KBD_CMD_RESET_ENABLE 0xF6 /* reset and enable scanning */
48 #define KBD_CMD_RESET 0xFF /* Reset */
49 #define KBD_CMD_SET_MAKE_BREAK 0xFC /* Set Make and Break mode */
[all …]
/qemu/hw/intc/
H A Dexynos4210_combiner.c46 ## __VA_ARGS__); } while (0)
48 #define DPRINTF(fmt, ...) do {} while (0)
51 #define IIC_REGION_SIZE 0x108 /* Size of memory mapped region */
69 VMSTATE_STRUCT_ARRAY(group, Exynos4210CombinerState, IIC_NGRP, 0,
99 val = 0; in exynos4210_combiner_read()
122 hw_error("exynos4210.combiner: overflow of reg_set by 0x" in exynos4210_combiner_read()
148 s->icipsr[0] |= 1 << group_n; in exynos4210_combiner_update()
164 s->icipsr[0] &= ~(1 << group_n); in exynos4210_combiner_update()
186 hw_error("exynos4210.combiner: unallowed write access at offset 0x" in exynos4210_combiner_write()
192 hw_error("exynos4210.combiner: unallowed write access at offset 0x" in exynos4210_combiner_write()
[all …]
/qemu/pc-bios/s390-ccw/
H A Dbootmap.h18 #define NULL_BLOCK_NR 0xffffffffffffffffULL
19 #define ERROR_BLOCK_NR 0xfffffffffffffffeULL
46 * it's 0 for TablePtr, ScriptPtr, and SectionPtr */
122 #define CMS1_MAGIC "\xc3\xd4\xe2\xf1" /* == "CMS1" in EBCDIC */
127 #define ZIPL_COMP_HEADER_IPL 0x00
128 #define ZIPL_COMP_HEADER_DUMP 0x01
130 #define ZIPL_COMP_ENTRY_EXEC 0x01
131 #define ZIPL_COMP_ENTRY_LOAD 0x02
132 #define ZIPL_COMP_ENTRY_SIGNATURE 0x03
139 #define DEV_TYPE_ECKD 0x00
[all …]

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