20 #define TEST_ADDR (0x10)
22 #define ADM1272_RESTART_TIME            0xCC
23 #define ADM1272_MFR_PEAK_IOUT           0xD0
24 #define ADM1272_MFR_PEAK_VIN            0xD1
25 #define ADM1272_MFR_PEAK_VOUT           0xD2
26 #define ADM1272_MFR_PMON_CONTROL        0xD3
27 #define ADM1272_MFR_PMON_CONFIG         0xD4
28 #define ADM1272_MFR_ALERT1_CONFIG       0xD5
29 #define ADM1272_MFR_ALERT2_CONFIG       0xD6
30 #define ADM1272_MFR_PEAK_TEMPERATURE    0xD7
31 #define ADM1272_MFR_DEVICE_CONFIG       0xD8
32 #define ADM1272_MFR_POWER_CYCLE         0xD9
33 #define ADM1272_MFR_PEAK_PIN            0xDA
34 #define ADM1272_MFR_READ_PIN_EXT        0xDB
35 #define ADM1272_MFR_READ_EIN_EXT        0xDC
37 #define ADM1272_HYSTERESIS_LOW          0xF2
38 #define ADM1272_HYSTERESIS_HIGH         0xF3
39 #define ADM1272_STATUS_HYSTERESIS       0xF4
40 #define ADM1272_STATUS_GPIO             0xF5
41 #define ADM1272_STRT_UP_IOUT_LIM        0xF6
44 #define ADM1272_OPERATION_DEFAULT       0x80
45 #define ADM1272_CAPABILITY_DEFAULT      0xB0
46 #define ADM1272_CAPABILITY_NO_PEC       0x30
47 #define ADM1272_DIRECT_MODE             0x40
48 #define ADM1272_HIGH_LIMIT_DEFAULT      0x0FFF
49 #define ADM1272_PIN_OP_DEFAULT          0x7FFF
50 #define ADM1272_PMBUS_REVISION_DEFAULT  0x22
55 #define ADM1272_RESTART_TIME_DEFAULT    0x64
56 #define ADM1272_PMON_CONTROL_DEFAULT    0x1
57 #define ADM1272_PMON_CONFIG_DEFAULT     0x3F35
58 #define ADM1272_DEVICE_CONFIG_DEFAULT   0x8
59 #define ADM1272_HYSTERESIS_HIGH_DEFAULT     0xFFFF
60 #define ADM1272_STRT_UP_IOUT_LIM_DEFAULT    0x000F
68 #define ADM1272_IOUT_OFFSET             0x5000
69 #define ADM1272_IOUT_OFFSET             0x5000
72     [0] = { 6770, 0, -2 },       /* voltage, vrange 60V */
73     [1] = { 4062, 0, -2 },       /* voltage, vrange 100V */
76     [4] = { 3512, 0, -2 },       /* power, vrange 60V, irange 15mV */
77     [5] = { 21071, 0, -3 },      /* power, vrange 100V, irange 15mV */
78     [6] = { 17561, 0, -3 },      /* power, vrange 60V, irange 30mV */
79     [7] = { 10535, 0, -3 },      /* power, vrange 100V, irange 30mV */
177     return (resp[1] << 8) | resp[0];  in adm1272_i2c_get16()
185     data[0] = value & 255;  in adm1272_i2c_set16()
209     g_assert_cmphex(i2c_value, ==, 0);  in test_defaults()
224     g_assert_cmphex(i2c_value, ==, 0);  in test_defaults()
298     adm1272_i2c_set16(i2cdev, PMBUS_VOUT_OV_WARN_LIMIT, 0xABCD);  in test_rw_regs()
300     g_assert_cmphex(i2c_value, ==, 0xABCD);  in test_rw_regs()
302     adm1272_i2c_set16(i2cdev, PMBUS_VOUT_UV_WARN_LIMIT, 0xCDEF);  in test_rw_regs()
304     g_assert_cmphex(i2c_value, ==, 0xCDEF);  in test_rw_regs()
306     adm1272_i2c_set16(i2cdev, PMBUS_IOUT_OC_WARN_LIMIT, 0x1234);  in test_rw_regs()
308     g_assert_cmphex(i2c_value, ==, 0x1234);  in test_rw_regs()
310     adm1272_i2c_set16(i2cdev, PMBUS_OT_FAULT_LIMIT, 0x5678);  in test_rw_regs()
312     g_assert_cmphex(i2c_value, ==, 0x5678);  in test_rw_regs()
314     adm1272_i2c_set16(i2cdev, PMBUS_OT_WARN_LIMIT, 0xABDC);  in test_rw_regs()
316     g_assert_cmphex(i2c_value, ==, 0xABDC);  in test_rw_regs()
318     adm1272_i2c_set16(i2cdev, PMBUS_VIN_OV_WARN_LIMIT, 0xCDEF);  in test_rw_regs()
320     g_assert_cmphex(i2c_value, ==, 0xCDEF);  in test_rw_regs()
322     adm1272_i2c_set16(i2cdev, PMBUS_VIN_UV_WARN_LIMIT, 0x2345);  in test_rw_regs()
324     g_assert_cmphex(i2c_value, ==, 0x2345);  in test_rw_regs()
326     i2c_set8(i2cdev, ADM1272_RESTART_TIME, 0xF8);  in test_rw_regs()
328     g_assert_cmphex(i2c_value, ==, 0xF8);  in test_rw_regs()
330     i2c_set8(i2cdev, ADM1272_MFR_PMON_CONTROL, 0);  in test_rw_regs()
332     g_assert_cmpuint(i2c_value, ==, 0);  in test_rw_regs()
334     adm1272_i2c_set16(i2cdev, ADM1272_MFR_PMON_CONFIG, 0xDEF0);  in test_rw_regs()
336     g_assert_cmphex(i2c_value, ==, 0xDEF0);  in test_rw_regs()
338     adm1272_i2c_set16(i2cdev, ADM1272_MFR_ALERT1_CONFIG, 0x0123);  in test_rw_regs()
340     g_assert_cmphex(i2c_value, ==, 0x0123);  in test_rw_regs()
342     adm1272_i2c_set16(i2cdev, ADM1272_MFR_ALERT2_CONFIG, 0x9876);  in test_rw_regs()
344     g_assert_cmphex(i2c_value, ==, 0x9876);  in test_rw_regs()
346     adm1272_i2c_set16(i2cdev, ADM1272_MFR_DEVICE_CONFIG, 0x3456);  in test_rw_regs()
348     g_assert_cmphex(i2c_value, ==, 0x3456);  in test_rw_regs()
350     adm1272_i2c_set16(i2cdev, ADM1272_HYSTERESIS_LOW, 0xCABA);  in test_rw_regs()
352     g_assert_cmphex(i2c_value, ==, 0xCABA);  in test_rw_regs()
354     adm1272_i2c_set16(i2cdev, ADM1272_HYSTERESIS_HIGH, 0x6789);  in test_rw_regs()
356     g_assert_cmphex(i2c_value, ==, 0x6789);  in test_rw_regs()
358     adm1272_i2c_set16(i2cdev, ADM1272_STRT_UP_IOUT_LIM, 0x9876);  in test_rw_regs()
360     g_assert_cmphex(i2c_value, ==, 0x9876);  in test_rw_regs()
362     adm1272_i2c_set16(i2cdev, PMBUS_OPERATION, 0xA);  in test_rw_regs()
364     g_assert_cmphex(i2c_value, ==, 0xA);  in test_rw_regs()
374     adm1272_i2c_set16(i2cdev, PMBUS_READ_VIN, 0xBEEF);  in test_ro_regs()
379     adm1272_i2c_set16(i2cdev, PMBUS_READ_VOUT, 0x1234);  in test_ro_regs()
384     adm1272_i2c_set16(i2cdev, PMBUS_READ_IOUT, 0x6547);  in test_ro_regs()
389     adm1272_i2c_set16(i2cdev, PMBUS_READ_TEMPERATURE_1, 0x1597);  in test_ro_regs()
394     adm1272_i2c_set16(i2cdev, PMBUS_READ_PIN, 0xDEAD);  in test_ro_regs()
412     g_assert_true((i2c_value & PB_STATUS_VOUT) != 0);  in test_voltage_faults()
413     g_assert_true((i2c_byte & PB_STATUS_VOUT_OV_WARN) != 0);  in test_voltage_faults()
416     i2c_set8(i2cdev, PMBUS_CLEAR_FAULTS, 0);  in test_voltage_faults()
418     g_assert_true((i2c_byte & PB_STATUS_VOUT_OV_WARN) == 0);  in test_voltage_faults()
424     g_assert_true((i2c_value & PB_STATUS_VOUT) != 0);  in test_voltage_faults()
425     g_assert_true((i2c_byte & PB_STATUS_VOUT_UV_WARN) != 0);  in test_voltage_faults()
432         .extra_device_opts = "id=" TEST_ID ",address=0x10"  in adm1272_register_nodes()