46                 ## __VA_ARGS__); } while (0)
48 #define DPRINTF(fmt, ...) do {} while (0)
51 #define IIC_REGION_SIZE    0x108         /* Size of memory mapped region */
69         VMSTATE_STRUCT_ARRAY(group, Exynos4210CombinerState, IIC_NGRP, 0,
99     val = 0;  in exynos4210_combiner_read()
122             hw_error("exynos4210.combiner: overflow of reg_set by 0x"  in exynos4210_combiner_read()
148             s->icipsr[0] |= 1 << group_n;  in exynos4210_combiner_update()
164             s->icipsr[0] &= ~(1 << group_n);  in exynos4210_combiner_update()
186         hw_error("exynos4210.combiner: unallowed write access at offset 0x"  in exynos4210_combiner_write()
192         hw_error("exynos4210.combiner: unallowed write access at offset 0x"  in exynos4210_combiner_write()
198         hw_error("exynos4210.combiner: overflow of reg_set by 0x"  in exynos4210_combiner_write()
205     case 0:  in exynos4210_combiner_write()
217         s->group[grp_quad_base_n].src_mask |= val & 0xFF;  in exynos4210_combiner_write()
218         s->group[grp_quad_base_n + 1].src_mask |= (val & 0xFF00) >> 8;  in exynos4210_combiner_write()
219         s->group[grp_quad_base_n + 2].src_mask |= (val & 0xFF0000) >> 16;  in exynos4210_combiner_write()
220         s->group[grp_quad_base_n + 3].src_mask |= (val & 0xFF000000) >> 24;  in exynos4210_combiner_write()
237         s->group[grp_quad_base_n].src_mask &= ~(val & 0xFF);  in exynos4210_combiner_write()
238         s->group[grp_quad_base_n + 1].src_mask &= ~((val & 0xFF00) >> 8);  in exynos4210_combiner_write()
239         s->group[grp_quad_base_n + 2].src_mask &= ~((val & 0xFF0000) >> 16);  in exynos4210_combiner_write()
240         s->group[grp_quad_base_n + 3].src_mask &= ~((val & 0xFF000000) >> 24);  in exynos4210_combiner_write()
248         hw_error("exynos4210.combiner: unallowed write access at offset 0x"  in exynos4210_combiner_write()
271         DPRINTF("%s unallowed IRQ group 0x%x\n", s->external ? "EXT" : "INT"  in exynos4210_combiner_handler()
289     memset(&s->group, 0, sizeof(s->group));  in exynos4210_combiner_reset()
290     memset(&s->reg_set, 0, sizeof(s->reg_set));  in exynos4210_combiner_reset()
292     s->reg_set[0xC0 >> 2] = 0x01010101;  in exynos4210_combiner_reset()
293     s->reg_set[0xC4 >> 2] = 0x01010101;  in exynos4210_combiner_reset()
294     s->reg_set[0xD0 >> 2] = 0x01010101;  in exynos4210_combiner_reset()
295     s->reg_set[0xD4 >> 2] = 0x01010101;  in exynos4210_combiner_reset()
319     for (i = 0; i < IIC_NGRP; i++) {  in exynos4210_combiner_init()
329     DEFINE_PROP_UINT32("external", Exynos4210CombinerState, external, 0),