Home
last modified time | relevance | path

Searched +full:0 +full:x80000 (Results 1 – 25 of 37) sorted by relevance

12

/qemu/tests/qemu-iotests/tests/
H A Dzoned.out5 start: 0x0, len 0x80000, cap 0x80000, wptr 0x0, zcond:1, [type: 2]
8 start: 0x0, len 0x80000, cap 0x80000, wptr 0x0, zcond:1, [type: 2]
9 start: 0x80000, len 0x80000, cap 0x80000, wptr 0x80000, zcond:1, [type: 2]
10 start: 0x100000, len 0x80000, cap 0x80000, wptr 0x100000, zcond:1, [type: 2]
11 start: 0x180000, len 0x80000, cap 0x80000, wptr 0x180000, zcond:1, [type: 2]
12 start: 0x200000, len 0x80000, cap 0x80000, wptr 0x200000, zcond:1, [type: 2]
13 start: 0x280000, len 0x80000, cap 0x80000, wptr 0x280000, zcond:1, [type: 2]
14 start: 0x300000, len 0x80000, cap 0x80000, wptr 0x300000, zcond:1, [type: 2]
15 start: 0x380000, len 0x80000, cap 0x80000, wptr 0x380000, zcond:1, [type: 2]
16 start: 0x400000, len 0x80000, cap 0x80000, wptr 0x400000, zcond:1, [type: 2]
[all …]
/qemu/tests/qemu-iotests/
H A D04625 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
60 local pattern=0
61 local cur_sec=0
63 for ((i=0;i<=$((sectors - 1));i++)); do
71 backing_io 0 32 write | $QEMU_IO "$TEST_IMG" | _filter_qemu_io
84 aio_write -P 10 0x18000 0x2000
87 aio_write -P 11 0x12000 0x2000
88 aio_write -P 12 0x1c000 0x2000
98 aio_write -P 20 0x28000 0x2000
[all …]
H A D07325 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
56 $QEMU_IO -c "write -P 0xa5 0 $size" "$TEST_IMG.base" | _filter_qemu_io
61 $QEMU_IO -c "write -P 0x11 0 0x10000" "$TEST_IMG" | _filter_qemu_io
62 $QEMU_IO -c "write -P 0x11 0x10000 0x10000" "$TEST_IMG.base" | _filter_qemu_io
64 $QEMU_IO -c "read -P 0x11 0 0x20000" "$TEST_IMG" | _filter_qemu_io
69 $QEMU_IO -c "write -P 0x22 0x20000 0x10000" "$TEST_IMG" | _filter_qemu_io
70 $QEMU_IO -c "write -c -P 0x22 0x30000 0x10000" "$TEST_IMG" | _filter_qemu_io
72 $QEMU_IO -c "read -P 0x22 0x20000 0x20000" "$TEST_IMG" | _filter_qemu_io
77 $QEMU_IO -c "write -P 0x33 0x40000 0x20000" "$TEST_IMG" | _filter_qemu_io
[all …]
H A D061.out6 wrote 131072/131072 bytes at offset 0
8 magic 0x514649fb
10 backing_file_offset 0x0
11 backing_file_size 0x0
14 crypt_method 0
16 l1_table_offset 0x30000
17 refcount_table_offset 0x10000
19 nb_snapshots 0
20 snapshot_offset 0x0
22 compatible_features [0]
[all …]
H A D271.out8 write -q -P PATTERN 0 1k
9 L2 entry #0: 0x8000000000050000 0000000000000001
11 L2 entry #0: 0x8000000000050000 0000000000000003
13 L2 entry #0: 0x8000000000050000 0000000000000007
15 L2 entry #0: 0x8000000000050000 000000000000000f
17 L2 entry #0: 0x8000000000050000 000000000000007f
19 L2 entry #0: 0x8000000000050000 00000000000003ff
21 L2 entry #0: 0x8000000000050000 00000000000103ff
23 L2 entry #0: 0x8000000000050000 00000000800103ff
24 L2 entry #1: 0x8000000000060000 0000000000000003
[all …]
H A D06025 seq="$(basename $0)"
34 trap "_cleanup; exit \$status" 0 1 2 3 15
60 rt_offset=65536 # 0x10000 (XXX: just an assumption)
61 rb_offset=131072 # 0x20000 (XXX: just an assumption)
62 l1_offset=196608 # 0x30000 (XXX: just an assumption)
63 l2_offset=262144 # 0x40000 (XXX: just an assumption)
64 l2_offset_after_snapshot=524288 # 0x80000 (XXX: just an assumption)
86 $QEMU_IO -c "$OPEN_RW" -c "write -P 0x2a 0 512" | _filter_qemu_io
95 $QEMU_IO -c "$OPEN_RW" -c "read 0 512" 2>&1 | _filter_qemu_io \
100 $QEMU_IO -c "$OPEN_RO" -c "read 0 512" | _filter_qemu_io
[all …]
/qemu/linux-user/mips/
H A Dtarget_mman.h4 #define TARGET_PROT_SEM 0x10
6 #define TARGET_MAP_NORESERVE 0x0400
7 #define TARGET_MAP_ANONYMOUS 0x0800
8 #define TARGET_MAP_GROWSDOWN 0x1000
9 #define TARGET_MAP_DENYWRITE 0x2000
10 #define TARGET_MAP_EXECUTABLE 0x4000
11 #define TARGET_MAP_LOCKED 0x8000
12 #define TARGET_MAP_POPULATE 0x10000
13 #define TARGET_MAP_NONBLOCK 0x20000
14 #define TARGET_MAP_STACK 0x40000
[all …]
/qemu/linux-user/xtensa/
H A Dtarget_mman.h4 #define TARGET_PROT_SEM 0x10
6 #define TARGET_MAP_NORESERVE 0x0400
7 #define TARGET_MAP_ANONYMOUS 0x0800
8 #define TARGET_MAP_GROWSDOWN 0x1000
9 #define TARGET_MAP_DENYWRITE 0x2000
10 #define TARGET_MAP_EXECUTABLE 0x4000
11 #define TARGET_MAP_LOCKED 0x8000
12 #define TARGET_MAP_POPULATE 0x10000
13 #define TARGET_MAP_NONBLOCK 0x20000
14 #define TARGET_MAP_STACK 0x40000
[all …]
/qemu/linux-user/alpha/
H A Dtarget_mman.h4 #define TARGET_MAP_ANONYMOUS 0x10
5 #define TARGET_MAP_FIXED 0x100
6 #define TARGET_MAP_GROWSDOWN 0x01000
7 #define TARGET_MAP_DENYWRITE 0x02000
8 #define TARGET_MAP_EXECUTABLE 0x04000
9 #define TARGET_MAP_LOCKED 0x08000
10 #define TARGET_MAP_NORESERVE 0x10000
11 #define TARGET_MAP_POPULATE 0x20000
12 #define TARGET_MAP_NONBLOCK 0x40000
13 #define TARGET_MAP_STACK 0x80000
[all …]
/qemu/linux-user/hppa/
H A Dtarget_mman.h4 #define TARGET_MAP_TYPE 0x2b
5 #define TARGET_MAP_FIXED 0x04
6 #define TARGET_MAP_ANONYMOUS 0x10
7 #define TARGET_MAP_GROWSDOWN 0x8000
8 #define TARGET_MAP_POPULATE 0x10000
9 #define TARGET_MAP_NONBLOCK 0x20000
10 #define TARGET_MAP_STACK 0x40000
11 #define TARGET_MAP_HUGETLB 0x80000
12 #define TARGET_MAP_UNINITIALIZED 0
28 #define TASK_UNMAPPED_BASE 0x40000000
[all …]
/qemu/target/i386/
H A Dsev.h22 #define sev_enabled() 0
23 #define sev_es_enabled() 0
24 #define sev_snp_enabled() 0
37 #define SEV_POLICY_NODBG 0x1
38 #define SEV_POLICY_NOKS 0x2
39 #define SEV_POLICY_ES 0x4
40 #define SEV_POLICY_NOSEND 0x8
41 #define SEV_POLICY_DOMAIN 0x10
42 #define SEV_POLICY_SEV 0x20
44 #define SEV_SNP_POLICY_SMT 0x10000
[all …]
/qemu/hw/display/
H A Ddpcd.c37 #define DPCD_READABLE_AREA 0x600
45 * The DCPD is 0x7FFFF length but read as 0 after offset 0x5FF.
60 qemu_log_mask(LOG_GUEST_ERROR, "dpcd: Bad offset 0x%" HWADDR_PRIX "\n", in dpcd_read()
62 ret = 0; in dpcd_read()
78 qemu_log_mask(LOG_GUEST_ERROR, "dpcd: Bad offset 0x%" HWADDR_PRIX "\n", in dpcd_write()
100 memset(&(s->dpcd_info), 0, sizeof(s->dpcd_info)); in dpcd_reset()
107 s->dpcd_info[DPCD_RECEIVE_PORT0_CAP_1] = 0xFF; in dpcd_reset()
130 memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x80000); in dpcd_init()
136 .version_id = 0,
137 .minimum_version_id = 0,
[all …]
/qemu/linux-headers/asm-mips/
H A Dmman.h18 #define PROT_NONE 0x00 /* page can not be accessed */
19 #define PROT_READ 0x01 /* page can be read */
20 #define PROT_WRITE 0x02 /* page can be written */
21 #define PROT_EXEC 0x04 /* page can be executed */
22 /* 0x08 reserved for PROT_EXEC_NOFLUSH */
23 #define PROT_SEM 0x10 /* page may be used for atomic ops */
24 #define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
25 #define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
30 /* 0x01 - 0x03 are defined in linux/mman.h */
31 #define MAP_TYPE 0x00f /* Mask for type of mapping */
[all …]
/qemu/target/xtensa/core-test_kc705_be/
H A Dxtensa-modules.c.inc31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
[all …]
/qemu/include/hw/arm/
H A Dxlnx-versal.h174 #define MM_TOP_RSVD 0xa0000000U
175 #define MM_TOP_RSVD_SIZE 0x4000000
176 #define MM_GIC_APU_DIST_MAIN 0xf9000000U
177 #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000
178 #define MM_GIC_APU_REDIST_0 0xf9080000U
179 #define MM_GIC_APU_REDIST_0_SIZE 0x80000
181 #define MM_UART0 0xff000000U
182 #define MM_UART0_SIZE 0x10000
183 #define MM_UART1 0xff010000U
184 #define MM_UART1_SIZE 0x10000
[all …]
/qemu/tests/qtest/libqos/
H A Dahci.h33 #define PCI_DEVICE_ID_INTEL_Q35_AHCI (0x2922)
34 #define PCI_MSI_FLAGS_RESERVED (0xFF00)
35 #define PCI_PM_CTRL_RESERVED (0xFC)
37 #define PCI_PI(REG32) (((REG32) >> 8) & 0xFF)
38 #define PCI_SCC(REG32) (((REG32) >> 16) & 0xFF)
45 #define AHCI_CAP (0)
46 #define AHCI_CAP_NP (0x1F)
47 #define AHCI_CAP_SXS (0x20)
48 #define AHCI_CAP_EMS (0x40)
49 #define AHCI_CAP_CCCS (0x80)
[all …]
/qemu/tcg/s390x/
H A Dtcg-target.c.inc48 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 16)
51 /* Several places within the instruction set 0 means "no register"
53 #define TCG_REG_NONE 0
66 RIL_AFI = 0xc209,
67 RIL_AGFI = 0xc208,
68 RIL_ALFI = 0xc20b,
69 RIL_ALGFI = 0xc20a,
70 RIL_BRASL = 0xc005,
71 RIL_BRCL = 0xc004,
72 RIL_CFI = 0xc20d,
[all …]
/qemu/hw/riscv/
H A Dopentitan.c42 [IBEX_DEV_ROM] = { 0x00008000, 0x8000 },
43 [IBEX_DEV_RAM] = { 0x10000000, 0x20000 },
44 [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 },
45 [IBEX_DEV_UART] = { 0x40000000, 0x40 },
46 [IBEX_DEV_GPIO] = { 0x40040000, 0x40 },
47 [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x2000 },
48 [IBEX_DEV_I2C] = { 0x40080000, 0x80 },
49 [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x40 },
50 [IBEX_DEV_TIMER] = { 0x40100000, 0x200 },
51 [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x2000 },
[all …]
/qemu/hw/mips/
H A Djazz.c72 address_space_read(&address_space_memory, 0x90000071, in rtc_read()
80 uint8_t buf = val & 0xff; in rtc_write()
81 address_space_write(&address_space_memory, 0x90000071, in rtc_write()
98 return 0xff; in dma_dummy_read()
138 sysbus_mmio_map(sysbus, 0, 0x80001000); in mips_jazz_init_net()
139 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); in mips_jazz_init_net()
143 checksum = 0; in mips_jazz_init_net()
144 for (i = 0; i < 6; i++) { in mips_jazz_init_net()
147 if (checksum > 0xff) { in mips_jazz_init_net()
148 checksum = (checksum + 1) & 0xff; in mips_jazz_init_net()
[all …]
H A Dloongson3_virt.c54 #define PM_CNTL_MODE 0x10
65 #define UART_IRQ 0
70 [VIRT_LOWMEM] = { 0x00000000, 0x10000000 },
71 [VIRT_PM] = { 0x10080000, 0x100 },
72 [VIRT_FW_CFG] = { 0x10080100, 0x100 },
73 [VIRT_RTC] = { 0x10081000, 0x1000 },
74 [VIRT_PCIE_PIO] = { 0x18000000, 0x80000 },
75 [VIRT_PCIE_ECAM] = { 0x1a000000, 0x2000000 },
76 [VIRT_BIOS_ROM] = { 0x1fc00000, 0x200000 },
77 [VIRT_UART] = { 0x1fe001e0, 0x8 },
[all …]
/qemu/hw/arm/
H A Draspi.c33 #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */
34 #define MVBAR_ADDR 0x400 /* secure vectors */
35 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
36 #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
37 #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
38 #define SPINTABLE_ADDR 0xd8 /* Pi 3 bootloader spintable */
51 FIELD(REV_CODE, REVISION, 0, 4);
59 PROCESSOR_ID_BCM2835 = 0,
118 { 0xe1a0e00f }, /* mov lr, pc */ in write_smpboot()
119 { 0xe3a0fe00 + (BOARDSETUP_ADDR >> 4) }, /* mov pc, BOARDSETUP_ADDR */ in write_smpboot()
[all …]
/qemu/hw/misc/macio/
H A Dmacio.c52 * Reference: ftp://ftp.software.ibm.com/rs6000/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
60 0x00, 0x00, /* Command B */ in macio_escc_legacy_setup()
61 0x02, 0x20, /* Command A */ in macio_escc_legacy_setup()
62 0x04, 0x10, /* Data B */ in macio_escc_legacy_setup()
63 0x06, 0x30, /* Data A */ in macio_escc_legacy_setup()
64 0x08, 0x40, /* Enhancement B */ in macio_escc_legacy_setup()
65 0x0A, 0x50, /* Enhancement A */ in macio_escc_legacy_setup()
66 0x80, 0x80, /* Recovery count */ in macio_escc_legacy_setup()
67 0x90, 0x90, /* Start A */ in macio_escc_legacy_setup()
68 0xa0, 0xa0, /* Start B */ in macio_escc_legacy_setup()
[all …]
/qemu/hw/pci-host/
H A Dppc440_pcix.c69 #define PPC440_REG_BASE 0x80000
70 #define PPC440_REG_SIZE 0xff
72 #define PCIC0_CFGADDR 0x0
73 #define PCIC0_CFGDATA 0x4
75 #define PCIX0_POM0LAL 0x68
76 #define PCIX0_POM0LAH 0x6c
77 #define PCIX0_POM0SA 0x70
78 #define PCIX0_POM0PCIAL 0x74
79 #define PCIX0_POM0PCIAH 0x78
80 #define PCIX0_POM1LAL 0x7c
[all …]
/qemu/hw/ppc/
H A Dsam460ex.c48 /* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \
51 #define PCIE0_DCRN_BASE 0x100
52 #define PCIE1_DCRN_BASE 0x120
55 #define FLASH_BASE 0xfff00000
56 #define FLASH_BASE_H 0x4
58 #define UBOOT_LOAD_BASE 0xfff80000
59 #define UBOOT_SIZE 0x00080000
60 #define UBOOT_ENTRY 0xfffffffc
63 #define EPAPR_MAGIC (0x45504150)
64 #define KERNEL_ADDR 0x1000000
[all …]
/qemu/include/block/
H A Dblock-common.h93 BLK_Z_NONE = 0x0, /* Regular block device */
94 BLK_Z_HM = 0x1, /* Host-managed zoned block device */
95 BLK_Z_HA = 0x2, /* Host-aware zoned block device */
99 BLK_ZS_NOT_WP = 0x0,
100 BLK_ZS_EMPTY = 0x1,
101 BLK_ZS_IOPEN = 0x2,
102 BLK_ZS_EOPEN = 0x3,
103 BLK_ZS_CLOSED = 0x4,
104 BLK_ZS_RDONLY = 0xD,
105 BLK_ZS_FULL = 0xE,
[all …]

12