hw/pci-host/ppc440_pcix.c

69 #define PPC440_REG_BASE     0x80000
70 #define PPC440_REG_SIZE     0xff
72 #define PCIC0_CFGADDR       0x0
73 #define PCIC0_CFGDATA       0x4
75 #define PCIX0_POM0LAL       0x68
76 #define PCIX0_POM0LAH       0x6c
77 #define PCIX0_POM0SA        0x70
78 #define PCIX0_POM0PCIAL     0x74
79 #define PCIX0_POM0PCIAH     0x78
80 #define PCIX0_POM1LAL       0x7c
81 #define PCIX0_POM1LAH       0x80
82 #define PCIX0_POM1SA        0x84
83 #define PCIX0_POM1PCIAL     0x88
84 #define PCIX0_POM1PCIAH     0x8c
85 #define PCIX0_POM2SA        0x90
87 #define PCIX0_PIM0SAL       0x98
88 #define PCIX0_PIM0LAL       0x9c
89 #define PCIX0_PIM0LAH       0xa0
90 #define PCIX0_PIM1SA        0xa4
91 #define PCIX0_PIM1LAL       0xa8
92 #define PCIX0_PIM1LAH       0xac
93 #define PCIX0_PIM2SAL       0xb0
94 #define PCIX0_PIM2LAL       0xb4
95 #define PCIX0_PIM2LAH       0xb8
96 #define PCIX0_PIM0SAH       0xf8
97 #define PCIX0_PIM2SAH       0xfc
99 #define PCIX0_STS           0xe0
131     memory_region_add_subregion_overlap(&s->bm, 0, mem, -1);  in ppc440_pcix_update_pim()
154     size = ~(s->pom[idx].sa & 0xfffffffe) + 1;  in ppc440_pcix_update_pom()
156         size = 0xffffffff;  in ppc440_pcix_update_pom()
178         s->pom[0].la &= 0xffffffff00000000ULL;  in ppc440_pcix_reg_write4()
179         s->pom[0].la |= val;  in ppc440_pcix_reg_write4()
180         ppc440_pcix_update_pom(s, 0);  in ppc440_pcix_reg_write4()
183         s->pom[0].la &= 0xffffffffULL;  in ppc440_pcix_reg_write4()
184         s->pom[0].la |= val << 32;  in ppc440_pcix_reg_write4()
185         ppc440_pcix_update_pom(s, 0);  in ppc440_pcix_reg_write4()
188         s->pom[0].sa = val;  in ppc440_pcix_reg_write4()
189         ppc440_pcix_update_pom(s, 0);  in ppc440_pcix_reg_write4()
192         s->pom[0].pcia &= 0xffffffff00000000ULL;  in ppc440_pcix_reg_write4()
193         s->pom[0].pcia |= val;  in ppc440_pcix_reg_write4()
194         ppc440_pcix_update_pom(s, 0);  in ppc440_pcix_reg_write4()
197         s->pom[0].pcia &= 0xffffffffULL;  in ppc440_pcix_reg_write4()
198         s->pom[0].pcia |= val << 32;  in ppc440_pcix_reg_write4()
199         ppc440_pcix_update_pom(s, 0);  in ppc440_pcix_reg_write4()
202         s->pom[1].la &= 0xffffffff00000000ULL;  in ppc440_pcix_reg_write4()
207         s->pom[1].la &= 0xffffffffULL;  in ppc440_pcix_reg_write4()
216         s->pom[1].pcia &= 0xffffffff00000000ULL;  in ppc440_pcix_reg_write4()
221         s->pom[1].pcia &= 0xffffffffULL;  in ppc440_pcix_reg_write4()
230         s->pim[0].sa &= 0xffffffff00000000ULL;  in ppc440_pcix_reg_write4()
231         s->pim[0].sa |= val;  in ppc440_pcix_reg_write4()
232         ppc440_pcix_update_pim(s, 0);  in ppc440_pcix_reg_write4()
235         s->pim[0].la &= 0xffffffff00000000ULL;  in ppc440_pcix_reg_write4()
236         s->pim[0].la |= val;  in ppc440_pcix_reg_write4()
237         ppc440_pcix_update_pim(s, 0);  in ppc440_pcix_reg_write4()
240         s->pim[0].la &= 0xffffffffULL;  in ppc440_pcix_reg_write4()
241         s->pim[0].la |= val << 32;  in ppc440_pcix_reg_write4()
242         ppc440_pcix_update_pim(s, 0);  in ppc440_pcix_reg_write4()
249         s->pim[1].la &= 0xffffffff00000000ULL;  in ppc440_pcix_reg_write4()
254         s->pim[1].la &= 0xffffffffULL;  in ppc440_pcix_reg_write4()
259         s->pim[2].sa &= 0xffffffff00000000ULL;  in ppc440_pcix_reg_write4()
264         s->pim[2].la &= 0xffffffff00000000ULL;  in ppc440_pcix_reg_write4()
269         s->pim[2].la &= 0xffffffffULL;  in ppc440_pcix_reg_write4()
279         s->pim[0].sa &= 0xffffffffULL;  in ppc440_pcix_reg_write4()
280         s->pim[0].sa |= val << 32;  in ppc440_pcix_reg_write4()
281         ppc440_pcix_update_pim(s, 0);  in ppc440_pcix_reg_write4()
284         s->pim[2].sa &= 0xffffffffULL;  in ppc440_pcix_reg_write4()
291                       "%s: unhandled PCI internal register 0x%"HWADDR_PRIx"\n",  in ppc440_pcix_reg_write4()
309         val = s->pom[0].la;  in ppc440_pcix_reg_read4()
312         val = s->pom[0].la >> 32;  in ppc440_pcix_reg_read4()
315         val = s->pom[0].sa;  in ppc440_pcix_reg_read4()
318         val = s->pom[0].pcia;  in ppc440_pcix_reg_read4()
321         val = s->pom[0].pcia >> 32;  in ppc440_pcix_reg_read4()
343         val = s->pim[0].sa;  in ppc440_pcix_reg_read4()
346         val = s->pim[0].la;  in ppc440_pcix_reg_read4()
349         val = s->pim[0].la >> 32;  in ppc440_pcix_reg_read4()
375         val = s->pim[0].sa  >> 32;  in ppc440_pcix_reg_read4()
383                       "%s: invalid PCI internal register 0x%" HWADDR_PRIx "\n",  in ppc440_pcix_reg_read4()
385         val = 0;  in ppc440_pcix_reg_read4()
403     for (i = 0; i < PPC440_PCIX_NR_POMS; i++) {  in ppc440_pcix_reset()
406     for (i = 0; i < PPC440_PCIX_NR_PIMS; i++) {  in ppc440_pcix_reset()
409     memset(s->pom, 0, sizeof(s->pom));  in ppc440_pcix_reset()
410     memset(s->pim, 0, sizeof(s->pim));  in ppc440_pcix_reset()
411     for (i = 0; i < PPC440_PCIX_NR_PIMS; i++) {  in ppc440_pcix_reset()
412         s->pim[i].sa = 0xffffffff00000000ULL;  in ppc440_pcix_reset()
414     s->sts = 0;  in ppc440_pcix_reset()
419  * IRQ, so our mapping function here maps everything to IRQ 0.
428     trace_ppc440_pcix_map_irq(pci_dev->devfn, irq_num, 0);  in ppc440_pcix_map_irq()
429     return 0;  in ppc440_pcix_map_irq()
437     if (irq_num < 0) {  in ppc440_pcix_set_irq()
466     if (addr != 0 || len != 4) {  in pci_host_config_write()
469     s->config_reg = (val & 0xfffffffcULL) | (1UL << 31);  in pci_host_config_write()
501                          PCI_DEVFN(1, 0), 1, TYPE_PCI_BUS);  in ppc440_pcix_realize()
504     memory_region_add_subregion(&s->bm, 0x0, &s->busmem);  in ppc440_pcix_realize()