33 #define SMPBOOT_ADDR    0x300 /* this should leave enough space for ATAGS */
34 #define MVBAR_ADDR      0x400 /* secure vectors */
35 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
36 #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
37 #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
38 #define SPINTABLE_ADDR  0xd8 /* Pi 3 bootloader spintable */
51 FIELD(REV_CODE, REVISION,           0, 4);
59     PROCESSOR_ID_BCM2835 = 0,
118         { 0xe1a0e00f }, /*    mov     lr, pc */  in write_smpboot()
119         { 0xe3a0fe00 + (BOARDSETUP_ADDR >> 4) }, /* mov pc, BOARDSETUP_ADDR */  in write_smpboot()
120         { 0xee100fb0 }, /*    mrc     p15, 0, r0, c0, c0, 5;get core ID */  in write_smpboot()
121         { 0xe7e10050 }, /*    ubfx    r0, r0, #0, #2       ;extract LSB */  in write_smpboot()
122         { 0xe59f5014 }, /*    ldr     r5, =0x400000CC      ;load mbox base */  in write_smpboot()
123         { 0xe320f001 }, /* 1: yield */  in write_smpboot()
124         { 0xe7953200 }, /*    ldr     r3, [r5, r0, lsl #4] ;read mbox for our core */  in write_smpboot()
125         { 0xe3530000 }, /*    cmp     r3, #0               ;spin while zero */  in write_smpboot()
126         { 0x0afffffb }, /*    beq     1b */  in write_smpboot()
127         { 0xe7853200 }, /*    str     r3, [r5, r0, lsl #4] ;clear mbox */  in write_smpboot()
128         { 0xe12fff13 }, /*    bx      r3                   ;jump to target */  in write_smpboot()
129         { 0x400000cc }, /* (constant: mailbox 3 read/clear base) */  in write_smpboot()
130         { 0, FIXUP_TERMINATOR }  in write_smpboot()
132     static const uint32_t fixupcontext[FIXUP_MAX] = { 0 };  in write_smpboot()
137     QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0  in write_smpboot()
138                       || (BOARDSETUP_ADDR >> 4) >= 0x100);  in write_smpboot()
150      * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for  in write_smpboot64()
156         { 0xd2801b05 }, /*        mov     x5, 0xd8 */  in write_smpboot64()
157         { 0xd53800a6 }, /*        mrs     x6, mpidr_el1 */  in write_smpboot64()
158         { 0x924004c6 }, /*        and     x6, x6, #0x3 */  in write_smpboot64()
159         { 0xd503205f }, /* spin:  wfe */  in write_smpboot64()
160         { 0xf86678a4 }, /*        ldr     x4, [x5,x6,lsl #3] */  in write_smpboot64()
161         { 0xb4ffffc4 }, /*        cbz     x4, spin */  in write_smpboot64()
162         { 0xd2800000 }, /*        mov     x0, #0x0 */  in write_smpboot64()
163         { 0xd2800001 }, /*        mov     x1, #0x0 */  in write_smpboot64()
164         { 0xd2800002 }, /*        mov     x2, #0x0 */  in write_smpboot64()
165         { 0xd2800003 }, /*        mov     x3, #0x0 */  in write_smpboot64()
166         { 0xd61f0080 }, /*        br      x4 */  in write_smpboot64()
167         { 0, FIXUP_TERMINATOR }  in write_smpboot64()
169     static const uint32_t fixupcontext[FIXUP_MAX] = { 0 };  in write_smpboot64()
172         0, 0, 0, 0  in write_smpboot64()
234         if (r < 0) {  in setup_boot()
267     memory_region_add_subregion_overlap(get_system_memory(), 0,  in raspi_base_machine_init()
268                                         machine->ram, 0);  in raspi_base_machine_init()
279     di = drive_get(IF_SD, 0, 0);  in raspi_base_machine_init()
295     if (vcram_base == 0) {  in raspi_base_machine_init()
300     setup_boot(machine, &soc->cpu[0].core, board_processor_id(board_rev),  in raspi_base_machine_init()
346     rmc->board_rev = 0x920092; /* Revision 1.2 */  in raspi0_machine_class_init()
356     rmc->board_rev = 0x900021; /* Revision 1.1 */  in raspi1ap_machine_class_init()
366     rmc->board_rev = 0xa21041;  in raspi2b_machine_class_init()
377     rmc->board_rev = 0x9020e0; /* Revision 1.0 */  in raspi3ap_machine_class_init()
387     rmc->board_rev = 0xa02082;  in raspi3b_machine_class_init()