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/qemu/tests/tcg/i386/
H A Dtest-i386-f2xm1.c14 { 0x4.1481697ac693aa6p-4L, 0x3.17ec9f8454896518p-4L, 0x3.17ec9f845489651cp-4L },
15 { -0xd.84a873b14b9c0e2p-4L, -0x7.1788c46ac260d948p-4L, -0x7.1788c46ac260d94p-4L },
16 { 0xa.a3dc18b1eff7e8ap-188L, 0x7.6009241b9e21523p-188L, 0x7.6009241b9e215238p-188L },
17 { -0xe.846aeb6f58174d5p-92L, -0xa.1006405817acc33p-92L, -0xa.1006405817acc32p-92L },
18 { 0x5.4459f2ac77bb0978p-4L, 0x4.19d3ce7fd5b90ac8p-4L, 0x4.19d3ce7fd5b90adp-4L },
19 { -0xb.79bece734a62216p-4L, -0x6.4489a7fc150c0fp-4L, -0x6.4489a7fc150c0ef8p-4L },
20 { 0xa.ab48f9ef732f5c4p-4L, 0x9.66acd7d4b7cf015p-4L, 0x9.66acd7d4b7cf016p-4L },
21 { -0xb.8204e63359a46e6p-4L, -0x6.48060f0a504e3488p-4L, -0x6.48060f0a504e348p-4L },
22 { 0xd.c732865701ae935p-4L, 0xd.103bc1a15cd9f71p-4L, 0xd.103bc1a15cd9f72p-4L },
23 { -0x1.6296e8ff499827a2p-4L, -0xe.e8dc973f0bce9d1p-8L, -0xe.e8dc973f0bce9dp-8L },
[all …]
H A Dtest-i386-fyl2x.c31 { 0x1p-16400L, 1.5L, -24600.0L, -24600.0L },
33 …{ 0x2.0a40b4bd6349d53p+14380L, -0x3.612a1cec52e70388p-14116L, -0xb.dd9637a24570d1ap-14104L, -0xb.d…
34 …{ 0xa.a3dc18b1eff7e8ap-4L, 0x7.423575b7ac0ba6a8p-7212L, -0x4.45ac6ae2f9cc1a7p-7212L, -0x4.45ac6ae2…
35 …{ 0x1.51167cab1deec25ep-9616L, 0xb.79bece734a62216p-14512L, -0x1.af0880f05109d5c8p-14496L, -0x1.af…
36 …{ 0x1.55691f3dee65eb88p+6420L, -0x2.e081398cd6691b98p-2640L, -0x4.8275aa22ebb6ebe8p-2628L, -0x4.82…
37 …{ 0x3.71cca195c06ba4d4p-6312L, -0xb.14b747fa4cc13d1p+5052L, 0x1.112301748a1cc83p+5068L, 0x1.112301…
38 …{ 0x2.0f924dde0806572p+8924L, -0x7.ece8699d62a9f76p-14464L, -0x1.144eba5c079d0fa2p-14448L, -0x1.14…
39 …{ 0x4.b875c0342c9f86b8p-5832L, 0xe.a37e0fa859e499cp+732L, -0x1.4d5bc95e2af0bb08p+748L, -0x1.4d5bc9…
40 …{ 0x7.23210d9474f0715p+364L, -0x5.baaf3a431730f158p-2436L, -0x8.35afbc04cd37fafp-2428L, -0x8.35afb…
41 …{ 0xd.2330923899aae43p+776L, 0x2.a68cc6ddbe3b3a5p+6528L, 0x8.12b3f5a7b346e37p+6536L, 0x8.12b3f5a7b…
[all …]
H A Dtest-i386-fyl2xp1.c26 { 0x4p-4L, 0x1p-16400L, 0x5.269e12f3468p-16404L, 0x5.269e12f347p-16404L },
28 …{ 0x1.31edb79669dd58b4p-4L, 0x6.c25439d8a5ce071p+14380L, 0xb.3d0da52c1f58af3p+14376L, 0xb.3d0da52c…
29 …{ -0x1.8ee6680c65ce5a5p-4L, -0x7.423575b7ac0ba6a8p-2228L, 0x1.12aefa96f5501268p-2228L, 0x1.12aefa9…
30 …{ 0x2.a22cf9563bdd84bcp-140L, -0x2.de6fb39cd2988858p-9616L, -0xa.e65ebedd6a09e4cp-9756L, -0xa.e65e…
31 …{ -0x7.d1095c8p-16416L, 0x1.faa600d255691f3cp+6420L, -0x1.6516c14a553da39ap-9992L, -0x1.6516c14a55…
32 …{ 0x4.109249df7871ecb8p-4L, 0x1.48d8eebeb8e650ccp-4976L, 0x6.b65f4ea303a8bc3p-4980L, 0x6.b65f4ea30…
33 …{ -0x4.69bcd5ccca0e4b7p-4L, -0x5.8808ae941f249bb8p+5056L, 0x2.93432047c7d8a37p+5056L, 0x2.93432047…
34 …{ 0x3.311f29ec8b38ef74p-4L, -0x3.9865a5505c3ae018p+8924L, -0xf.188d6a2bba06e17p+8920L, -0xf.188d6a…
35 …{ -0x2.d60110be2e4f812p-4L, 0x9.d61827e646421b3p-11580L, -0x2.c4c3e84b6c7366c8p-11580L, -0x2.c4c3e…
36 …{ 0xe.e4d7ebcee10774ap-8L, 0x6.5cde5b7691984918p+732L, 0x8.4e3d353f31e18a3p+728L, 0x8.4e3d353f31e1…
[all …]
H A Dtest-i386-fpatan.c10 { -__builtin_infl(), -__builtin_infl(), -0x2.5b2f8fe6643a46ap+0L, -0x2.5b2f8fe6643a469cp+0L },
11 { -__builtin_infl(), -1.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
12 { -__builtin_infl(), -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
13 { -__builtin_infl(), 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
14 { -__builtin_infl(), 1.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
15 { -__builtin_infl(), __builtin_infl(), 0x2.5b2f8fe6643a469cp+0L, 0x2.5b2f8fe6643a46ap+0L },
16 { -1.0L, -__builtin_infl(), -0x1.921fb54442d1846ap+0L, -0x1.921fb54442d18468p+0L },
17 { -1.0L, -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
18 { -1.0L, 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
19 { -1.0L, __builtin_infl(), 0x1.921fb54442d18468p+0L, 0x1.921fb54442d1846ap+0L },
[all …]
/qemu/target/riscv/
H A Dinstmap.h22 #define MASK_OP_MAJOR(op) (op & 0x7F)
25 OPC_RISC_LUI = (0x37),
26 OPC_RISC_AUIPC = (0x17),
27 OPC_RISC_JAL = (0x6F),
28 OPC_RISC_JALR = (0x67),
29 OPC_RISC_BRANCH = (0x63),
30 OPC_RISC_LOAD = (0x03),
31 OPC_RISC_STORE = (0x23),
32 OPC_RISC_ARITH_IMM = (0x13),
33 OPC_RISC_ARITH = (0x33),
[all …]
/qemu/include/hw/misc/
H A Dimx31_ccm.h17 #define IMX31_CCM_CCMR_REG 0
46 #define CCMR_FPME (1<<0)
55 #define PDR0_MCU_PODF_SHIFT (0)
56 #define PDR0_MCU_PODF_MASK (0x7)
58 #define PDR0_MAX_PODF_MASK (0x7)
60 #define PDR0_IPG_PODF_MASK (0x3)
62 #define PDR0_NFC_PODF_MASK (0x7)
64 #define PDR0_HSP_PODF_MASK (0x7)
66 #define PDR0_PER_PODF_MASK (0x1f)
68 #define PDR0_CSI_PODF_MASK (0x1ff)
H A Daspeed_scu.h26 #define ASPEED_SCU_NR_REGS (0x1A8 >> 2)
27 #define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2)
28 #define ASPEED_AST2700_SCU_NR_REGS (0xE20 >> 2)
44 #define AST2400_A0_SILICON_REV 0x02000303U
45 #define AST2400_A1_SILICON_REV 0x02010303U
46 #define AST2500_A0_SILICON_REV 0x04000303U
47 #define AST2500_A1_SILICON_REV 0x04010303U
48 #define AST2600_A0_SILICON_REV 0x05000303U
49 #define AST2600_A1_SILICON_REV 0x05010303U
50 #define AST2600_A2_SILICON_REV 0x05020303U
[all …]
/qemu/hw/mips/
H A Dboston.c54 #define FDT_IRQ_TYPE_NONE 0
56 #define FDT_GIC_SHARED 0
99 [BOSTON_LOWDDR] = { 0x0, 0x10000000 },
100 [BOSTON_PCIE0] = { 0x10000000, 0x2000000 },
101 [BOSTON_PCIE1] = { 0x12000000, 0x2000000 },
102 [BOSTON_PCIE2] = { 0x14000000, 0x2000000 },
103 [BOSTON_PCIE2_MMIO] = { 0x16000000, 0x100000 },
104 [BOSTON_CM] = { 0x16100000, 0x20000 },
105 [BOSTON_GIC] = { 0x16120000, 0x20000 },
106 [BOSTON_CDMM] = { 0x16140000, 0x8000 },
[all …]
/qemu/tests/unit/
H A Dtest-fifo.c24 uint8_t data_in1[] = { 0x1, 0x2, 0x3, 0x4 }; in test_fifo8_pop_bufptr_wrap()
25 uint8_t data_in2[] = { 0x5, 0x6, 0x7, 0x8, 0x9, 0xa }; in test_fifo8_pop_bufptr_wrap()
31 * head --v-- tail used = 0 in test_fifo8_pop_bufptr_wrap()
47 g_assert(buf[0] == 0x1 && buf[1] == 0x2); in test_fifo8_pop_bufptr_wrap()
61 g_assert(buf[0] == 0x3 && buf[1] == 0x4 && buf[2] == 0x5 && in test_fifo8_pop_bufptr_wrap()
62 buf[3] == 0x6 && buf[4] == 0x7 && buf[5] == 0x8); in test_fifo8_pop_bufptr_wrap()
71 uint8_t data_in[] = { 0x1, 0x2, 0x3, 0x4 }; in test_fifo8_pop_bufptr()
77 * head --v-- tail used = 0 in test_fifo8_pop_bufptr()
93 g_assert(buf[0] == 0x1 && buf[1] == 0x2); in test_fifo8_pop_bufptr()
102 uint8_t data_in1[] = { 0x1, 0x2, 0x3, 0x4 }; in test_fifo8_peek_bufptr_wrap()
[all …]
/qemu/target/mips/tcg/
H A Dmips16e_translate.c.inc14 M16_OPC_ADDIUSP = 0x00,
15 M16_OPC_ADDIUPC = 0x01,
16 M16_OPC_B = 0x02,
17 M16_OPC_JAL = 0x03,
18 M16_OPC_BEQZ = 0x04,
19 M16_OPC_BNEQZ = 0x05,
20 M16_OPC_SHIFT = 0x06,
21 M16_OPC_LD = 0x07,
22 M16_OPC_RRIA = 0x08,
23 M16_OPC_ADDIU8 = 0x09,
[all …]
H A Dmicromips_translate.c.inc25 POOL32A = 0x00,
26 POOL16A = 0x01,
27 LBU16 = 0x02,
28 MOVE16 = 0x03,
29 ADDI32 = 0x04,
30 R6_LUI = 0x04,
31 AUI = 0x04,
32 LBU32 = 0x05,
33 SB32 = 0x06,
34 LB32 = 0x07,
[all …]
/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_fmov.c.inc12 TCGv zero = tcg_constant_tl(0);
139 tcg_gen_deposit_i64(dest, dest, src, 0, 32);
164 tcg_gen_andi_tl(t0, src, 0x1);
165 tcg_gen_st8_tl(t0, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
181 offsetof(CPULoongArchState, cf[a->cj & 0x7]));
198 tcg_gen_andi_tl(t0, gpr_src(ctx, a->rj, EXT_NONE), 0x1);
199 tcg_gen_st8_tl(t0, tcg_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
213 offsetof(CPULoongArchState, cf[a->cj & 0x7]));
/qemu/hw/sd/
H A Dsdmmc-internal.h117 #define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
118 #define EXT_CSD_PART_CONFIG_ACC_DEFAULT (0x0)
119 #define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
121 #define EXT_CSD_PART_CONFIG_EN_MASK (0x7 << 3)
122 #define EXT_CSD_PART_CONFIG_EN_BOOT0 (0x1 << 3)
123 #define EXT_CSD_PART_CONFIG_EN_USER (0x7 << 3)
/qemu/tests/tcg/s390x/
H A Dcvb.c19 #define FAIL 0x1234567887654321
20 #define OK32(x) (0x1234567800000000 | (uint32_t)(x))
54 __uint128_t m = (((__uint128_t)0x9223372036854775) << 16) | 0x8070; in main()
58 memset(&act, 0, sizeof(act)); in main()
61 assert(err == 0); in main()
63 assert(err == 0); in main()
65 assert(cvb(0xc) == OK32(0) && signum == -1); in main()
66 assert(cvb(0x1c) == OK32(1) && signum == -1); in main()
67 assert(cvb(0x25594c) == OK32(25594) && signum == -1); in main()
68 assert(cvb(0x1d) == OK32(-1) && signum == -1); in main()
[all …]
/qemu/hw/intc/
H A Driscv_aclint.c138 } else if ((addr & 0x7) == 0) { in riscv_aclint_mtimer_read()
141 return (size == 4) ? (timecmp & 0xFFFFFFFF) : timecmp; in riscv_aclint_mtimer_read()
142 } else if ((addr & 0x7) == 4) { in riscv_aclint_mtimer_read()
145 return (timecmp >> 32) & 0xFFFFFFFF; in riscv_aclint_mtimer_read()
149 return 0; in riscv_aclint_mtimer_read()
154 return (size == 4) ? (rtc & 0xFFFFFFFF) : rtc; in riscv_aclint_mtimer_read()
157 return (cpu_riscv_read_rtc(mtimer) >> 32) & 0xFFFFFFFF; in riscv_aclint_mtimer_read()
162 return 0; in riscv_aclint_mtimer_read()
181 } else if ((addr & 0x7) == 0) { in riscv_aclint_mtimer_write()
186 timecmp_hi << 32 | (value & 0xFFFFFFFF)); in riscv_aclint_mtimer_write()
[all …]
H A Dioapic_internal.h56 #define IOAPIC_TRIGGER_EDGE 0
60 #define IOAPIC_DM_FIXED 0x0
61 #define IOAPIC_DM_LOWEST_PRIORITY 0x1
62 #define IOAPIC_DM_PMI 0x2
63 #define IOAPIC_DM_NMI 0x4
64 #define IOAPIC_DM_INIT 0x5
65 #define IOAPIC_DM_SIPI 0x6
66 #define IOAPIC_DM_EXTINT 0x7
67 #define IOAPIC_DM_MASK 0x7
69 #define IOAPIC_VECTOR_MASK 0xff
[all …]
/qemu/include/hw/char/
H A Dsifive_uart.h30 SIFIVE_UART_TXFIFO = 0,
52 #define SIFIVE_UART_TXFIFO_FULL 0x80000000
54 #define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7)
55 #define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7)
/qemu/tests/qtest/
H A Dfuzz-megasas-test.c25 qtest_outl(s, 0xcf8, 0x80001818); in test_lp1878263_megasas_zero_iov_cnt()
26 qtest_outl(s, 0xcfc, 0xc101); in test_lp1878263_megasas_zero_iov_cnt()
27 qtest_outl(s, 0xcf8, 0x8000181c); in test_lp1878263_megasas_zero_iov_cnt()
28 qtest_outl(s, 0xcf8, 0x80001804); in test_lp1878263_megasas_zero_iov_cnt()
29 qtest_outw(s, 0xcfc, 0x7); in test_lp1878263_megasas_zero_iov_cnt()
30 qtest_outl(s, 0xcf8, 0x8000186a); in test_lp1878263_megasas_zero_iov_cnt()
31 qtest_writeb(s, 0x14, 0xfe); in test_lp1878263_megasas_zero_iov_cnt()
32 qtest_writeb(s, 0x0, 0x02); in test_lp1878263_megasas_zero_iov_cnt()
33 qtest_outb(s, 0xc1c0, 0x17); in test_lp1878263_megasas_zero_iov_cnt()
48 qtest_outl(s, 0xcf8, 0x80000818); in test_gitlab_issue521_megasas_sgl_ovf()
[all …]
H A Dfuzz-lsi53c895a-test.c25 qtest_outl(s, 0xcf8, 0x80000804); /* PCI Command Register */ in test_lsi_dma_reentrancy()
26 qtest_outw(s, 0xcfc, 0x7); /* Enables accesses */ in test_lsi_dma_reentrancy()
27 qtest_outl(s, 0xcf8, 0x80000814); /* Memory Bar 1 */ in test_lsi_dma_reentrancy()
28 qtest_outl(s, 0xcfc, 0xff100000); /* Set MMIO Address*/ in test_lsi_dma_reentrancy()
29 qtest_outl(s, 0xcf8, 0x80000818); /* Memory Bar 2 */ in test_lsi_dma_reentrancy()
30 qtest_outl(s, 0xcfc, 0xff000000); /* Set RAM Address*/ in test_lsi_dma_reentrancy()
31 qtest_writel(s, 0xff000000, 0xc0000024); in test_lsi_dma_reentrancy()
32 qtest_writel(s, 0xff000114, 0x00000080); in test_lsi_dma_reentrancy()
33 qtest_writel(s, 0xff00012c, 0xff000000); in test_lsi_dma_reentrancy()
34 qtest_writel(s, 0xff000004, 0xff000114); in test_lsi_dma_reentrancy()
[all …]
/qemu/hw/display/
H A Dmacfb.c25 #define VIDEO_BASE 0x0
26 #define DAFB_BASE 0x00800000
31 #define DAFB_MODE_VADDR1 0x0
32 #define DAFB_MODE_VADDR2 0x4
33 #define DAFB_MODE_CTRL1 0x8
34 #define DAFB_MODE_CTRL2 0xc
35 #define DAFB_MODE_SENSE 0x1c
36 #define DAFB_INTR_MASK 0x104
37 #define DAFB_INTR_STAT 0x108
38 #define DAFB_INTR_CLEAR 0x10c
[all …]
/qemu/include/hw/scsi/
H A Desp.h83 #define ESP_TCLO 0x0
84 #define ESP_TCMID 0x1
85 #define ESP_FIFO 0x2
86 #define ESP_CMD 0x3
87 #define ESP_RSTAT 0x4
88 #define ESP_WBUSID 0x4
89 #define ESP_RINTR 0x5
90 #define ESP_WSEL 0x5
91 #define ESP_RSEQ 0x6
92 #define ESP_WSYNTP 0x6
[all …]
/qemu/common-user/host/aarch64/
H A Dsafe-syscall.inc.S32 * x2 ... x7, (stack) == syscall arguments
47 mov x5, x7
61 svc 0x0
68 b.hi 0f
79 0: neg w0, w0
/qemu/include/block/
H A Dnvme.h82 CAP_MQES_SHIFT = 0,
96 CAP_MQES_MASK = 0xffff,
97 CAP_CQR_MASK = 0x1,
98 CAP_AMS_MASK = 0x3,
99 CAP_TO_MASK = 0xff,
100 CAP_DSTRD_MASK = 0xf,
101 CAP_NSSRS_MASK = 0x1,
102 CAP_CSS_MASK = 0xff,
103 CAP_MPSMIN_MASK = 0xf,
104 CAP_MPSMAX_MASK = 0xf,
[all …]
/qemu/pc-bios/keymaps/
H A Dsv1 map 0x0000041d
3 Shift_R 0x36
4 Shift_L 0x2a
6 Alt_R 0xb8
7 Mode_switch 0xb8
8 ISO_Level3_Shift 0xb8
9 Alt_L 0x38
11 Control_R 0x9d
12 Control_L 0x1d
16 Super_R 0xdc
[all …]
/qemu/hw/net/fsl_etsec/
H A Detsec.c53 } while (0)
82 uint32_t ret = 0x0; in etsec_read()
91 ret = 0x00000000; in etsec_read()
102 DPRINTF("Read 0x%08x @ 0x" HWADDR_FMT_plx in etsec_read()
114 int i = 0; in write_tstat()
116 for (i = 0; i < 8; i++) { in write_tstat()
132 int i = 0; in write_rstat()
134 for (i = 0; i < 8; i++) { in write_rstat()
150 reg->value = value & ~0x7; in write_tbasex()
153 etsec->regs[TBPTR0 + (reg_index - TBASE0)].value = value & ~0x7; in write_tbasex()
[all …]

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