Lines Matching +full:0 +full:x7
26 #define ASPEED_SCU_NR_REGS (0x1A8 >> 2)
27 #define ASPEED_AST2600_SCU_NR_REGS (0xE20 >> 2)
28 #define ASPEED_AST2700_SCU_NR_REGS (0xE20 >> 2)
44 #define AST2400_A0_SILICON_REV 0x02000303U
45 #define AST2400_A1_SILICON_REV 0x02010303U
46 #define AST2500_A0_SILICON_REV 0x04000303U
47 #define AST2500_A1_SILICON_REV 0x04010303U
48 #define AST2600_A0_SILICON_REV 0x05000303U
49 #define AST2600_A1_SILICON_REV 0x05010303U
50 #define AST2600_A2_SILICON_REV 0x05020303U
51 #define AST2600_A3_SILICON_REV 0x05030303U
52 #define AST1030_A0_SILICON_REV 0x80000000U
53 #define AST1030_A1_SILICON_REV 0x80010000U
54 #define AST2700_A0_SILICON_REV 0x06000103U
55 #define AST2720_A0_SILICON_REV 0x06000203U
56 #define AST2750_A0_SILICON_REV 0x06000003U
57 #define AST2700_A1_SILICON_REV 0x06010103U
58 #define AST2750_A1_SILICON_REV 0x06010003U
60 #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
77 #define ASPEED_SCU_PROT_KEY 0x1688A8A8
117 * 0 CPU/AHB clock dynamic slow down enable (defined in bit[6:4])
119 #define SCU_CLK_GET_PCLK_DIV(x) (((x) >> 23) & 0x7)
125 * 0: Select H-PLL by strapping resistors
126 * 1: Select H-PLL by the programmed registers (SCU24[17:0])
131 * 3:0 H-PLL Denumerator
136 #define SCU_AST2400_H_PLL_PROGRAMMED (0x1 << 18)
137 #define SCU_AST2400_H_PLL_BYPASS_EN (0x1 << 17)
138 #define SCU_AST2400_H_PLL_OFF (0x1 << 16)
148 * 4:0 H-PLL Denumerator (N)
155 #define SCU_H_PLL_BYPASS_EN (0x1 << 20)
156 #define SCU_H_PLL_OFF (0x1 << 19)
167 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address
182 * 1:0 BMC CPU boot code selection
185 #define SCU_AST2400_HW_STRAP_SW_DEFINE_MASK (0x7 << 29)
188 #define SCU_AST2400_HW_STRAP_DRAM_SIZE_MASK (0x3 << 27)
189 #define DRAM_SIZE_64MB 0
195 #define SCU_AST2400_HW_STRAP_DRAM_CONFIG_MASK (0x7 << 24)
197 #define SCU_HW_STRAP_GPIOE_PT_EN (0x1 << 22)
198 #define SCU_HW_STRAP_GPIOD_PT_EN (0x1 << 21)
199 #define SCU_HW_STRAP_LPC_DEC_SUPER_IO (0x1 << 20)
200 #define SCU_AST2400_HW_STRAP_ACPI_DIS (0x1 << 19)
202 /* bit 23, 18 [1,0] */
203 #define SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(x) (((((x) & 0x3) >> 1) << 23) \
204 | (((x) & 0x1) << 18))
205 #define SCU_AST2400_HW_STRAP_GET_CLK_SOURCE(x) (((((x) >> 23) & 0x1) << 1) \
206 | (((x) >> 18) & 0x1))
207 #define SCU_AST2400_HW_STRAP_CLK_SOURCE_MASK ((0x1 << 23) | (0x1 << 18))
208 #define SCU_HW_STRAP_CLK_25M_IN (0x1 << 23)
209 #define AST2400_CLK_24M_IN 0
214 #define SCU_HW_STRAP_CLK_48M_IN (0x1 << 18)
215 #define SCU_HW_STRAP_2ND_BOOT_WDT (0x1 << 17)
216 #define SCU_HW_STRAP_SUPER_IO_CONFIG (0x1 << 16)
217 #define SCU_HW_STRAP_VGA_CLASS_CODE (0x1 << 15)
218 #define SCU_HW_STRAP_LPC_RESET_PIN (0x1 << 14)
221 #define SCU_HW_STRAP_SPI_MODE_MASK (0x3 << 12)
222 #define SCU_HW_STRAP_SPI_DIS 0
229 #define SCU_AST2400_HW_STRAP_CPU_AHB_RATIO_MASK (0x3 << 10)
230 #define AST2400_CPU_AHB_RATIO_1_1 0
235 #define SCU_AST2400_HW_STRAP_GET_H_PLL_CLK(x) (((x) >> 8) & 0x3)
236 #define SCU_AST2400_HW_STRAP_H_PLL_CLK_MASK (0x3 << 8)
237 #define AST2400_CPU_384MHZ 0
242 #define SCU_HW_STRAP_MAC1_RGMII (0x1 << 7)
243 #define SCU_HW_STRAP_MAC0_RGMII (0x1 << 6)
244 #define SCU_HW_STRAP_VGA_BIOS_ROM (0x1 << 5)
245 #define SCU_HW_STRAP_SPI_WIDTH (0x1 << 4)
247 #define SCU_HW_STRAP_VGA_SIZE_GET(x) (((x) >> 2) & 0x3)
248 #define SCU_HW_STRAP_VGA_MASK (0x3 << 2)
250 #define VGA_8M_DRAM 0
256 #define AST2400_NOR_BOOT 0
276 * 20 Disable LPC to decode SuperIO 0x2E/0x4E address
285 * 8 Reserved (0)
289 * 4 Reserved (0)
292 * 0 Disable CPU boot
294 #define SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE (0x1 << 31)
295 #define SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE (0x1 << 30)
296 #define SCU_AST2500_HW_STRAP_UART_DEBUG (0x1 << 29)
297 #define UART_DEBUG_UART1 0
299 #define SCU_AST2500_HW_STRAP_RESERVED28 (0x1 << 28)
301 #define SCU_AST2500_HW_STRAP_FAST_RESET_DBG (0x1 << 27)
302 #define SCU_AST2500_HW_STRAP_ESPI_FLASH_ENABLE (0x1 << 26)
303 #define SCU_AST2500_HW_STRAP_ESPI_ENABLE (0x1 << 25)
304 #define SCU_AST2500_HW_STRAP_DDR4_ENABLE (0x1 << 24)
305 #define SCU_AST2500_HW_STRAP_25HZ_CLOCK_MODE (0x1 << 23)
307 #define SCU_AST2500_HW_STRAP_ACPI_ENABLE (0x1 << 19)
308 #define SCU_AST2500_HW_STRAP_USBCKI_FREQ (0x1 << 18)
309 #define USBCKI_FREQ_24MHZ 0
314 #define SCU_AST2500_HW_STRAP_CPU_AXI_RATIO_MASK (0x7 << 9)
315 #define AXI_AHB_RATIO_UNDEFINED 0
324 #define SCU_AST2500_HW_STRAP_RESERVED1 (0x1 << 1)
325 #define SCU_AST2500_HW_STRAP_DIS_BOOT (0x1 << 0)
345 * 12:0 H-PLL Denumerator (N)
351 #define SCU_AST2600_H_PLL_BYPASS_EN (0x1 << 24)
352 #define SCU_AST2600_H_PLL_OFF (0x1 << 23)
355 #define SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC (0x1 << 2)
356 #define SCU_AST2600_HW_STRAP_BOOT_SRC_SPI (0x0 << 2)
376 * 0 Select UART1 clock source
378 #define SCU_AST1030_CLK_GET_PCLK_DIV(x) (((x) >> 8) & 0xf)
403 * 0 UART1CLK_SEL
405 #define SCUIO_AST2700_CLK_GET_PCLK_DIV(x) (((x) >> 18) & 0x7)