xref: /qemu/hw/intc/ioapic_internal.h (revision 8be545ba5a315a9aaf7307f143a4a7926a6e605c)
1244ac3afSJan Kiszka /*
2244ac3afSJan Kiszka  *  IOAPIC emulation logic - internal interfaces
3244ac3afSJan Kiszka  *
4244ac3afSJan Kiszka  *  Copyright (c) 2004-2005 Fabrice Bellard
5244ac3afSJan Kiszka  *  Copyright (c) 2009      Xiantao Zhang, Intel
6244ac3afSJan Kiszka  *  Copyright (c) 2011 Jan Kiszka, Siemens AG
7244ac3afSJan Kiszka  *
8244ac3afSJan Kiszka  * This library is free software; you can redistribute it and/or
9244ac3afSJan Kiszka  * modify it under the terms of the GNU Lesser General Public
10244ac3afSJan Kiszka  * License as published by the Free Software Foundation; either
1161f3c91aSChetan Pant  * version 2.1 of the License, or (at your option) any later version.
12244ac3afSJan Kiszka  *
13244ac3afSJan Kiszka  * This library is distributed in the hope that it will be useful,
14244ac3afSJan Kiszka  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15244ac3afSJan Kiszka  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16244ac3afSJan Kiszka  * Lesser General Public License for more details.
17244ac3afSJan Kiszka  *
18244ac3afSJan Kiszka  * You should have received a copy of the GNU Lesser General Public
19244ac3afSJan Kiszka  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20244ac3afSJan Kiszka  */
21244ac3afSJan Kiszka 
227f54640bSBernhard Beschow #ifndef HW_INTC_IOAPIC_INTERNAL_H
237f54640bSBernhard Beschow #define HW_INTC_IOAPIC_INTERNAL_H
24244ac3afSJan Kiszka 
25*8be545baSRichard Henderson #include "system/memory.h"
267f54640bSBernhard Beschow #include "hw/intc/ioapic.h"
2783c9f4caSPaolo Bonzini #include "hw/sysbus.h"
28e3d9c925SPeter Xu #include "qemu/notify.h"
29db1015e9SEduardo Habkost #include "qom/object.h"
30244ac3afSJan Kiszka 
3194c5a606SGerd Hoffmann #define MAX_IOAPICS                     2
32244ac3afSJan Kiszka 
33244ac3afSJan Kiszka #define IOAPIC_LVT_DEST_SHIFT           56
34cb135f59SPeter Xu #define IOAPIC_LVT_DEST_IDX_SHIFT       48
35244ac3afSJan Kiszka #define IOAPIC_LVT_MASKED_SHIFT         16
36244ac3afSJan Kiszka #define IOAPIC_LVT_TRIGGER_MODE_SHIFT   15
37244ac3afSJan Kiszka #define IOAPIC_LVT_REMOTE_IRR_SHIFT     14
38244ac3afSJan Kiszka #define IOAPIC_LVT_POLARITY_SHIFT       13
39244ac3afSJan Kiszka #define IOAPIC_LVT_DELIV_STATUS_SHIFT   12
40244ac3afSJan Kiszka #define IOAPIC_LVT_DEST_MODE_SHIFT      11
41244ac3afSJan Kiszka #define IOAPIC_LVT_DELIV_MODE_SHIFT     8
42244ac3afSJan Kiszka 
43244ac3afSJan Kiszka #define IOAPIC_LVT_MASKED               (1 << IOAPIC_LVT_MASKED_SHIFT)
44af599407SPavel Butsykin #define IOAPIC_LVT_TRIGGER_MODE         (1 << IOAPIC_LVT_TRIGGER_MODE_SHIFT)
45244ac3afSJan Kiszka #define IOAPIC_LVT_REMOTE_IRR           (1 << IOAPIC_LVT_REMOTE_IRR_SHIFT)
46af599407SPavel Butsykin #define IOAPIC_LVT_POLARITY             (1 << IOAPIC_LVT_POLARITY_SHIFT)
47af599407SPavel Butsykin #define IOAPIC_LVT_DELIV_STATUS         (1 << IOAPIC_LVT_DELIV_STATUS_SHIFT)
48af599407SPavel Butsykin #define IOAPIC_LVT_DEST_MODE            (1 << IOAPIC_LVT_DEST_MODE_SHIFT)
49af599407SPavel Butsykin #define IOAPIC_LVT_DELIV_MODE           (7 << IOAPIC_LVT_DELIV_MODE_SHIFT)
50244ac3afSJan Kiszka 
51479c2a1cSPeter Xu /* Bits that are read-only for IOAPIC entry */
52479c2a1cSPeter Xu #define IOAPIC_RO_BITS                  (IOAPIC_LVT_REMOTE_IRR | \
53479c2a1cSPeter Xu                                          IOAPIC_LVT_DELIV_STATUS)
54479c2a1cSPeter Xu #define IOAPIC_RW_BITS                  (~(uint64_t)IOAPIC_RO_BITS)
55479c2a1cSPeter Xu 
56244ac3afSJan Kiszka #define IOAPIC_TRIGGER_EDGE             0
57244ac3afSJan Kiszka #define IOAPIC_TRIGGER_LEVEL            1
58244ac3afSJan Kiszka 
59244ac3afSJan Kiszka /*io{apic,sapic} delivery mode*/
60244ac3afSJan Kiszka #define IOAPIC_DM_FIXED                 0x0
61244ac3afSJan Kiszka #define IOAPIC_DM_LOWEST_PRIORITY       0x1
62244ac3afSJan Kiszka #define IOAPIC_DM_PMI                   0x2
63244ac3afSJan Kiszka #define IOAPIC_DM_NMI                   0x4
64244ac3afSJan Kiszka #define IOAPIC_DM_INIT                  0x5
65244ac3afSJan Kiszka #define IOAPIC_DM_SIPI                  0x6
66244ac3afSJan Kiszka #define IOAPIC_DM_EXTINT                0x7
67244ac3afSJan Kiszka #define IOAPIC_DM_MASK                  0x7
68244ac3afSJan Kiszka 
69244ac3afSJan Kiszka #define IOAPIC_VECTOR_MASK              0xff
70244ac3afSJan Kiszka 
71244ac3afSJan Kiszka #define IOAPIC_IOREGSEL                 0x00
72244ac3afSJan Kiszka #define IOAPIC_IOWIN                    0x10
7320fd4b7bSPeter Xu #define IOAPIC_EOI                      0x40
74244ac3afSJan Kiszka 
75244ac3afSJan Kiszka #define IOAPIC_REG_ID                   0x00
76244ac3afSJan Kiszka #define IOAPIC_REG_VER                  0x01
77244ac3afSJan Kiszka #define IOAPIC_REG_ARB                  0x02
78244ac3afSJan Kiszka #define IOAPIC_REG_REDTBL_BASE          0x10
79244ac3afSJan Kiszka #define IOAPIC_ID                       0x00
80244ac3afSJan Kiszka 
81244ac3afSJan Kiszka #define IOAPIC_ID_SHIFT                 24
82244ac3afSJan Kiszka #define IOAPIC_ID_MASK                  0xf
83244ac3afSJan Kiszka 
84244ac3afSJan Kiszka #define IOAPIC_VER_ENTRIES_SHIFT        16
85244ac3afSJan Kiszka 
86244ac3afSJan Kiszka 
87999e12bbSAnthony Liguori #define TYPE_IOAPIC_COMMON "ioapic-common"
88a489d195SEduardo Habkost OBJECT_DECLARE_TYPE(IOAPICCommonState, IOAPICCommonClass, IOAPIC_COMMON)
89999e12bbSAnthony Liguori 
90db1015e9SEduardo Habkost struct IOAPICCommonClass {
91999e12bbSAnthony Liguori     SysBusDeviceClass parent_class;
92db0f8888Sxiaoqiang zhao 
93db0f8888Sxiaoqiang zhao     DeviceRealize realize;
94958a01daSVitaly Kuznetsov     DeviceUnrealize unrealize;
95999e12bbSAnthony Liguori     void (*pre_save)(IOAPICCommonState *s);
96999e12bbSAnthony Liguori     void (*post_load)(IOAPICCommonState *s);
97db1015e9SEduardo Habkost };
98999e12bbSAnthony Liguori 
99244ac3afSJan Kiszka struct IOAPICCommonState {
100244ac3afSJan Kiszka     SysBusDevice busdev;
101244ac3afSJan Kiszka     MemoryRegion io_memory;
102244ac3afSJan Kiszka     uint8_t id;
103244ac3afSJan Kiszka     uint8_t ioregsel;
104244ac3afSJan Kiszka     uint32_t irr;
105244ac3afSJan Kiszka     uint64_t ioredtbl[IOAPIC_NUM_PINS];
106e3d9c925SPeter Xu     Notifier machine_done;
10720fd4b7bSPeter Xu     uint8_t version;
108cce5405eSPeter Xu     uint64_t irq_count[IOAPIC_NUM_PINS];
109cce5405eSPeter Xu     int irq_level[IOAPIC_NUM_PINS];
110958a01daSVitaly Kuznetsov     int irq_eoi[IOAPIC_NUM_PINS];
111958a01daSVitaly Kuznetsov     QEMUTimer *delayed_ioapic_service_timer;
112244ac3afSJan Kiszka };
113244ac3afSJan Kiszka 
114244ac3afSJan Kiszka void ioapic_reset_common(DeviceState *dev);
115244ac3afSJan Kiszka 
116cce5405eSPeter Xu void ioapic_stat_update_irq(IOAPICCommonState *s, int irq, int level);
117d665d696SPavel Butsykin 
1187f54640bSBernhard Beschow #endif /* HW_INTC_IOAPIC_INTERNAL_H */
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