xref: /qemu/include/hw/misc/imx31_ccm.h (revision 4dad0a9aa818698e0735c8352bf7925a1660df6f)
1cb54d868SJean-Christophe Dubois /*
2cb54d868SJean-Christophe Dubois  * IMX31 Clock Control Module
3cb54d868SJean-Christophe Dubois  *
4cb54d868SJean-Christophe Dubois  * Copyright (C) 2012 NICTA
5cb54d868SJean-Christophe Dubois  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
6cb54d868SJean-Christophe Dubois  *
7cb54d868SJean-Christophe Dubois  * This work is licensed under the terms of the GNU GPL, version 2 or later.
8cb54d868SJean-Christophe Dubois  * See the COPYING file in the top-level directory.
9cb54d868SJean-Christophe Dubois  */
10cb54d868SJean-Christophe Dubois 
11cb54d868SJean-Christophe Dubois #ifndef IMX31_CCM_H
12cb54d868SJean-Christophe Dubois #define IMX31_CCM_H
13cb54d868SJean-Christophe Dubois 
14cb54d868SJean-Christophe Dubois #include "hw/misc/imx_ccm.h"
15db1015e9SEduardo Habkost #include "qom/object.h"
16cb54d868SJean-Christophe Dubois 
17fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_CCMR_REG  0
18fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_PDR0_REG  1
19fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_PDR1_REG  2
20fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_RCSR_REG  3
21fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_MPCTL_REG 4
22fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_UPCTL_REG 5
23fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_SPCTL_REG 6
24fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_COSR_REG  7
25fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_CGR0_REG  8
26fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_CGR1_REG  9
27fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_CGR2_REG  10
28fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_WIMR_REG  11
29fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_LDC_REG   12
30fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_DCVR0_REG 13
31fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_DCVR1_REG 14
32fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_DCVR2_REG 15
33fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_DCVR3_REG 16
34fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_LTR0_REG  17
35fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_LTR1_REG  18
36fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_LTR2_REG  19
37fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_LTR3_REG  20
38fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_LTBR0_REG 21
39fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_LTBR1_REG 22
40fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_PMCR0_REG 23
41fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_PMCR1_REG 24
42fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_PDR2_REG  25
43fea01f96SJean-Christophe DUBOIS #define IMX31_CCM_MAX_REG   26
44fea01f96SJean-Christophe DUBOIS 
45cb54d868SJean-Christophe Dubois /* CCMR */
46cb54d868SJean-Christophe Dubois #define CCMR_FPME    (1<<0)
47cb54d868SJean-Christophe Dubois #define CCMR_MPE     (1<<3)
48cb54d868SJean-Christophe Dubois #define CCMR_MDS     (1<<7)
49cb54d868SJean-Christophe Dubois #define CCMR_FPMF    (1<<26)
50cb54d868SJean-Christophe Dubois #define CCMR_PRCS    (3<<1)
51cb54d868SJean-Christophe Dubois 
52cb54d868SJean-Christophe Dubois #define PMCR0_DFSUP1 (1<<31)
53cb54d868SJean-Christophe Dubois 
54cb54d868SJean-Christophe Dubois /* PDR0 */
55cb54d868SJean-Christophe Dubois #define PDR0_MCU_PODF_SHIFT (0)
56cb54d868SJean-Christophe Dubois #define PDR0_MCU_PODF_MASK (0x7)
57cb54d868SJean-Christophe Dubois #define PDR0_MAX_PODF_SHIFT (3)
58cb54d868SJean-Christophe Dubois #define PDR0_MAX_PODF_MASK (0x7)
59cb54d868SJean-Christophe Dubois #define PDR0_IPG_PODF_SHIFT (6)
60cb54d868SJean-Christophe Dubois #define PDR0_IPG_PODF_MASK (0x3)
61cb54d868SJean-Christophe Dubois #define PDR0_NFC_PODF_SHIFT (8)
62cb54d868SJean-Christophe Dubois #define PDR0_NFC_PODF_MASK (0x7)
63cb54d868SJean-Christophe Dubois #define PDR0_HSP_PODF_SHIFT (11)
64cb54d868SJean-Christophe Dubois #define PDR0_HSP_PODF_MASK (0x7)
65cb54d868SJean-Christophe Dubois #define PDR0_PER_PODF_SHIFT (16)
66cb54d868SJean-Christophe Dubois #define PDR0_PER_PODF_MASK (0x1f)
67cb54d868SJean-Christophe Dubois #define PDR0_CSI_PODF_SHIFT (23)
68cb54d868SJean-Christophe Dubois #define PDR0_CSI_PODF_MASK (0x1ff)
69cb54d868SJean-Christophe Dubois 
70cb54d868SJean-Christophe Dubois #define EXTRACT(value, name) (((value) >> PDR0_##name##_PODF_SHIFT) \
71cb54d868SJean-Christophe Dubois                               & PDR0_##name##_PODF_MASK)
72cb54d868SJean-Christophe Dubois #define INSERT(value, name) (((value) & PDR0_##name##_PODF_MASK) << \
73cb54d868SJean-Christophe Dubois                              PDR0_##name##_PODF_SHIFT)
74cb54d868SJean-Christophe Dubois 
75cb54d868SJean-Christophe Dubois #define TYPE_IMX31_CCM "imx31.ccm"
76*8063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(IMX31CCMState, IMX31_CCM)
77cb54d868SJean-Christophe Dubois 
78db1015e9SEduardo Habkost struct IMX31CCMState {
79cb54d868SJean-Christophe Dubois     /* <private> */
80cb54d868SJean-Christophe Dubois     IMXCCMState parent_obj;
81cb54d868SJean-Christophe Dubois 
82cb54d868SJean-Christophe Dubois     /* <public> */
83cb54d868SJean-Christophe Dubois     MemoryRegion iomem;
84cb54d868SJean-Christophe Dubois 
85fea01f96SJean-Christophe DUBOIS     uint32_t reg[IMX31_CCM_MAX_REG];
86fea01f96SJean-Christophe DUBOIS 
87db1015e9SEduardo Habkost };
88cb54d868SJean-Christophe Dubois 
89cb54d868SJean-Christophe Dubois #endif /* IMX31_CCM_H */
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