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/qemu/tests/tcg/i386/
H A Dtest-i386-f2xm1.c14 { 0x4.1481697ac693aa6p-4L, 0x3.17ec9f8454896518p-4L, 0x3.17ec9f845489651cp-4L },
15 { -0xd.84a873b14b9c0e2p-4L, -0x7.1788c46ac260d948p-4L, -0x7.1788c46ac260d94p-4L },
16 { 0xa.a3dc18b1eff7e8ap-188L, 0x7.6009241b9e21523p-188L, 0x7.6009241b9e215238p-188L },
17 { -0xe.846aeb6f58174d5p-92L, -0xa.1006405817acc33p-92L, -0xa.1006405817acc32p-92L },
18 { 0x5.4459f2ac77bb0978p-4L, 0x4.19d3ce7fd5b90ac8p-4L, 0x4.19d3ce7fd5b90adp-4L },
19 { -0xb.79bece734a62216p-4L, -0x6.4489a7fc150c0fp-4L, -0x6.4489a7fc150c0ef8p-4L },
20 { 0xa.ab48f9ef732f5c4p-4L, 0x9.66acd7d4b7cf015p-4L, 0x9.66acd7d4b7cf016p-4L },
21 { -0xb.8204e63359a46e6p-4L, -0x6.48060f0a504e3488p-4L, -0x6.48060f0a504e348p-4L },
22 { 0xd.c732865701ae935p-4L, 0xd.103bc1a15cd9f71p-4L, 0xd.103bc1a15cd9f72p-4L },
23 { -0x1.6296e8ff499827a2p-4L, -0xe.e8dc973f0bce9d1p-8L, -0xe.e8dc973f0bce9dp-8L },
[all …]
H A Dtest-i386-fyl2xp1.c26 { 0x4p-4L, 0x1p-16400L, 0x5.269e12f3468p-16404L, 0x5.269e12f347p-16404L },
28 …{ 0x1.31edb79669dd58b4p-4L, 0x6.c25439d8a5ce071p+14380L, 0xb.3d0da52c1f58af3p+14376L, 0xb.3d0da52c…
29 …{ -0x1.8ee6680c65ce5a5p-4L, -0x7.423575b7ac0ba6a8p-2228L, 0x1.12aefa96f5501268p-2228L, 0x1.12aefa9…
30 …{ 0x2.a22cf9563bdd84bcp-140L, -0x2.de6fb39cd2988858p-9616L, -0xa.e65ebedd6a09e4cp-9756L, -0xa.e65e…
31 …{ -0x7.d1095c8p-16416L, 0x1.faa600d255691f3cp+6420L, -0x1.6516c14a553da39ap-9992L, -0x1.6516c14a55…
32 …{ 0x4.109249df7871ecb8p-4L, 0x1.48d8eebeb8e650ccp-4976L, 0x6.b65f4ea303a8bc3p-4980L, 0x6.b65f4ea30…
33 …{ -0x4.69bcd5ccca0e4b7p-4L, -0x5.8808ae941f249bb8p+5056L, 0x2.93432047c7d8a37p+5056L, 0x2.93432047…
34 …{ 0x3.311f29ec8b38ef74p-4L, -0x3.9865a5505c3ae018p+8924L, -0xf.188d6a2bba06e17p+8920L, -0xf.188d6a…
35 …{ -0x2.d60110be2e4f812p-4L, 0x9.d61827e646421b3p-11580L, -0x2.c4c3e84b6c7366c8p-11580L, -0x2.c4c3e…
36 …{ 0xe.e4d7ebcee10774ap-8L, 0x6.5cde5b7691984918p+732L, 0x8.4e3d353f31e18a3p+728L, 0x8.4e3d353f31e1…
[all …]
H A Dtest-i386-fyl2x.c31 { 0x1p-16400L, 1.5L, -24600.0L, -24600.0L },
33 …{ 0x2.0a40b4bd6349d53p+14380L, -0x3.612a1cec52e70388p-14116L, -0xb.dd9637a24570d1ap-14104L, -0xb.d…
34 …{ 0xa.a3dc18b1eff7e8ap-4L, 0x7.423575b7ac0ba6a8p-7212L, -0x4.45ac6ae2f9cc1a7p-7212L, -0x4.45ac6ae2…
35 …{ 0x1.51167cab1deec25ep-9616L, 0xb.79bece734a62216p-14512L, -0x1.af0880f05109d5c8p-14496L, -0x1.af…
36 …{ 0x1.55691f3dee65eb88p+6420L, -0x2.e081398cd6691b98p-2640L, -0x4.8275aa22ebb6ebe8p-2628L, -0x4.82…
37 …{ 0x3.71cca195c06ba4d4p-6312L, -0xb.14b747fa4cc13d1p+5052L, 0x1.112301748a1cc83p+5068L, 0x1.112301…
38 …{ 0x2.0f924dde0806572p+8924L, -0x7.ece8699d62a9f76p-14464L, -0x1.144eba5c079d0fa2p-14448L, -0x1.14…
39 …{ 0x4.b875c0342c9f86b8p-5832L, 0xe.a37e0fa859e499cp+732L, -0x1.4d5bc95e2af0bb08p+748L, -0x1.4d5bc9…
40 …{ 0x7.23210d9474f0715p+364L, -0x5.baaf3a431730f158p-2436L, -0x8.35afbc04cd37fafp-2428L, -0x8.35afb…
41 …{ 0xd.2330923899aae43p+776L, 0x2.a68cc6ddbe3b3a5p+6528L, 0x8.12b3f5a7b346e37p+6536L, 0x8.12b3f5a7b…
[all …]
H A Dtest-i386-fpatan.c10 { -__builtin_infl(), -__builtin_infl(), -0x2.5b2f8fe6643a46ap+0L, -0x2.5b2f8fe6643a469cp+0L },
11 { -__builtin_infl(), -1.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
12 { -__builtin_infl(), -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
13 { -__builtin_infl(), 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
14 { -__builtin_infl(), 1.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
15 { -__builtin_infl(), __builtin_infl(), 0x2.5b2f8fe6643a469cp+0L, 0x2.5b2f8fe6643a46ap+0L },
16 { -1.0L, -__builtin_infl(), -0x1.921fb54442d1846ap+0L, -0x1.921fb54442d18468p+0L },
17 { -1.0L, -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L },
18 { -1.0L, 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L },
19 { -1.0L, __builtin_infl(), 0x1.921fb54442d18468p+0L, 0x1.921fb54442d1846ap+0L },
[all …]
/qemu/tests/qtest/migration/aarch64/
H A Da-b-kernel.S23 bic x0, x0, #(1<<0)
37 mov w3, #0
38 mov x4, x0
40 strb w3, [x4]
41 add x4, x4, #TEST_MEM_PAGE_SIZE
42 cmp x4, x1
46 mov w5, #0
50 mov x4, x0
54 ldrb w3, [x4]
56 strb w3, [x4]
[all …]
/qemu/pc-bios/dtb/
H A Dcanyonlands.dts18 dcr-parent = <&{/cpus/cpu@0}>;
29 #size-cells = <0>;
31 cpu@0 {
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
[all …]
/qemu/tests/tcg/tricore/asm/
H A Dtest_insert.S7 TEST_D_DIDI(insert, 1, 0x7fffffff, 0xffffffff, 0xa, 0x10, 0x8)
11 TEST_D_DIII(insert, 2, 0xd38fe370, 0xd38fe370, 0x4, 0x4 , 0x0)
12 TEST_D_DIII(insert, 3, 0xd38fe374, 0xd38fe370, 0x4, 0x0 , 0x4)
16 TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
20 TEST_D_DIE(insert, 5, 0xe30c308d, 0xe30c308d ,0x3 , 0x00000000 ,0x00000000)
21 TEST_D_DIE(insert, 6, 0x669b0120, 0x669b2820 ,0x2 , 0x5530a1c7 ,0x3a2b0f67)
/qemu/include/hw/timer/
H A Dallwinner-a10-pit.h12 #define AW_A10_PIT_TIMER_IRQ 0x1
13 #define AW_A10_PIT_WDOG_IRQ 0x100
15 #define AW_A10_PIT_TIMER_IRQ_EN 0
16 #define AW_A10_PIT_TIMER_IRQ_ST 0x4
18 #define AW_A10_PIT_TIMER_CONTROL 0x0
19 #define AW_A10_PIT_TIMER_EN 0x1
20 #define AW_A10_PIT_TIMER_RELOAD 0x2
21 #define AW_A10_PIT_TIMER_MODE 0x80
23 #define AW_A10_PIT_TIMER_INTERVAL 0x4
24 #define AW_A10_PIT_TIMER_COUNT 0x8
[all …]
/qemu/include/hw/scsi/
H A Desp.h83 #define ESP_TCLO 0x0
84 #define ESP_TCMID 0x1
85 #define ESP_FIFO 0x2
86 #define ESP_CMD 0x3
87 #define ESP_RSTAT 0x4
88 #define ESP_WBUSID 0x4
89 #define ESP_RINTR 0x5
90 #define ESP_WSEL 0x5
91 #define ESP_RSEQ 0x6
92 #define ESP_WSYNTP 0x6
[all …]
/qemu/tests/unit/
H A Dtest-fifo.c24 uint8_t data_in1[] = { 0x1, 0x2, 0x3, 0x4 }; in test_fifo8_pop_bufptr_wrap()
25 uint8_t data_in2[] = { 0x5, 0x6, 0x7, 0x8, 0x9, 0xa }; in test_fifo8_pop_bufptr_wrap()
31 * head --v-- tail used = 0 in test_fifo8_pop_bufptr_wrap()
47 g_assert(buf[0] == 0x1 && buf[1] == 0x2); in test_fifo8_pop_bufptr_wrap()
61 g_assert(buf[0] == 0x3 && buf[1] == 0x4 && buf[2] == 0x5 && in test_fifo8_pop_bufptr_wrap()
62 buf[3] == 0x6 && buf[4] == 0x7 && buf[5] == 0x8); in test_fifo8_pop_bufptr_wrap()
71 uint8_t data_in[] = { 0x1, 0x2, 0x3, 0x4 }; in test_fifo8_pop_bufptr()
77 * head --v-- tail used = 0 in test_fifo8_pop_bufptr()
93 g_assert(buf[0] == 0x1 && buf[1] == 0x2); in test_fifo8_pop_bufptr()
102 uint8_t data_in1[] = { 0x1, 0x2, 0x3, 0x4 }; in test_fifo8_peek_bufptr_wrap()
[all …]
/qemu/target/riscv/
H A Dsbi_ecall_interface.h15 #define SBI_SUCCESS 0
27 #define SBI_EXT_0_1_SET_TIMER 0x0
28 #define SBI_EXT_0_1_CONSOLE_PUTCHAR 0x1
29 #define SBI_EXT_0_1_CONSOLE_GETCHAR 0x2
30 #define SBI_EXT_0_1_CLEAR_IPI 0x3
31 #define SBI_EXT_0_1_SEND_IPI 0x4
32 #define SBI_EXT_0_1_REMOTE_FENCE_I 0x5
33 #define SBI_EXT_0_1_REMOTE_SFENCE_VMA 0x6
34 #define SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID 0x7
35 #define SBI_EXT_0_1_SHUTDOWN 0x8
[all …]
H A Dinstmap.h22 #define MASK_OP_MAJOR(op) (op & 0x7F)
25 OPC_RISC_LUI = (0x37),
26 OPC_RISC_AUIPC = (0x17),
27 OPC_RISC_JAL = (0x6F),
28 OPC_RISC_JALR = (0x67),
29 OPC_RISC_BRANCH = (0x63),
30 OPC_RISC_LOAD = (0x03),
31 OPC_RISC_STORE = (0x23),
32 OPC_RISC_ARITH_IMM = (0x13),
33 OPC_RISC_ARITH = (0x33),
[all …]
/qemu/tests/tcg/openrisc/
H A Dtest_lx.c9 result = 0x23; in main()
11 ("l.ori r8, r0, 0x123\n\t" in main()
12 "l.sb 0x4 + %1, r8\n\t" in main()
14 "l.lbz %0, 0x4 + %1\n\t" in main()
22 result = 0x23; in main()
24 ("l.lbs %0, 0x4 + %1\n\t" in main()
33 result = 0x1111; in main()
35 ("l.ori r8, r0, 0x1111\n\t" in main()
36 "l.sh 0x20 + %1, r8\n\t" in main()
38 "l.lhs %0, 0x20 + %1\n\t" in main()
[all …]
H A Dtest_divu.c8 b = 0x120; in main()
9 c = 0x4; in main()
10 result = 0x48; in main()
13 ("l.divu %0, %1, %2\n\t" in main()
22 result = 0x4; in main()
24 ("l.divu %0, %1, %0\n\t" in main()
33 return 0; in main()
H A Dtest_muli.c8 b = 0x4; in main()
9 c = 0x1; in main()
10 result = 0x4; in main()
12 ("l.muli %0, %1, 0x1\n\t" in main()
21 b = 0x1; in main()
22 c = 0x0; in main()
23 result = 0x0; in main()
25 ("l.muli %0, %1, 0x0\n\t" in main()
34 b = 0x1; in main()
35 c = 0xff; in main()
[all …]
H A Dtest_mulu.c8 b = 0x4; in main()
9 c = 0x1; in main()
10 result = 0x4; in main()
12 ("l.mulu %0, %1, %2\n\t" in main()
21 b = 0x1; in main()
22 c = 0x0; in main()
23 result = 0x0; in main()
25 ("l.mulu %0, %1, %2\n\t" in main()
34 b = 0x1; in main()
35 c = 0xff; in main()
[all …]
H A Dtest_div.c8 b = 0x120; in main()
9 c = 0x4; in main()
10 result = 0x48; in main()
12 ("l.div %0, %1, %2\n\t" in main()
21 result = 0x4; in main()
23 ("l.div %0, %1, %0\n\t" in main()
32 b = 0xffffffff; in main()
33 c = 0x80000000; in main()
34 result = 0; in main()
36 ("l.div %0, %1, %2\n\t" in main()
[all …]
H A Dtest_mul.c8 b = 0x4; in main()
9 c = 0x1; in main()
10 result = 0x4; in main()
12 ("l.mul %0, %1, %2\n\t" in main()
21 b = 0x1; in main()
22 c = 0x0; in main()
23 result = 0x0; in main()
25 ("l.mul %0, %1, %2\n\t" in main()
34 b = 0x1; in main()
35 c = 0xff; in main()
[all …]
/qemu/hw/sparc64/
H A Dsun4u_iommu.c41 #define IOMMU_CTRL 0x0
47 #define IOMMU_BASE 0x8
48 #define IOMMU_FLUSH 0x10
54 #define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL
55 #define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL
57 #define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL
58 #define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL
59 #define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL
60 #define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL
61 #define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL
[all …]
/qemu/target/ppc/translate/
H A Dvmx-ops.c.inc2 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
5 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
8 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300)
11 GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
14 GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \
18 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA310)
21 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
24 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, tp0, tp1), \
25 GEN_HANDLER_E(name0##_##name1, 0x4, opc2, (opc3 | 0x10), 0x00000000, tp0, tp1),
27 GEN_VXFORM_DUAL(vaddubm, vmul10cuq, 0, 0, PPC_ALTIVEC, PPC_NONE),
[all …]
/qemu/tests/qtest/
H A Dnvme-test.c59 qpci_io_writel(pdev, bar, 0, 0xccbbaa99); in nvmetest_oob_cmb_test()
60 g_assert_cmpint(qpci_io_readb(pdev, bar, 0), ==, 0x99); in nvmetest_oob_cmb_test()
61 g_assert_cmpint(qpci_io_readw(pdev, bar, 0), ==, 0xaa99); in nvmetest_oob_cmb_test()
64 qpci_io_writel(pdev, bar, cmb_bar_size - 1, 0x44332211); in nvmetest_oob_cmb_test()
65 g_assert_cmpint(qpci_io_readb(pdev, bar, cmb_bar_size - 1), ==, 0x11); in nvmetest_oob_cmb_test()
66 g_assert_cmpint(qpci_io_readw(pdev, bar, cmb_bar_size - 1), !=, 0x2211); in nvmetest_oob_cmb_test()
67 g_assert_cmpint(qpci_io_readl(pdev, bar, cmb_bar_size - 1), !=, 0x44332211); in nvmetest_oob_cmb_test()
79 bar = qpci_iomap(pdev, 0, NULL); in nvmetest_reg_read_test()
81 cap_lo = qpci_io_readl(pdev, bar, 0x0); in nvmetest_reg_read_test()
82 g_assert_cmpint(NVME_CAP_MQES(cap_lo), ==, 0x7ff); in nvmetest_reg_read_test()
[all …]
H A Dpvpanic-pci-test.c33 dev = qpci_device_find(pcibus, QPCI_DEVFN(0x4, 0x0)); in test_panic_nopause()
35 bar = qpci_iomap(dev, 0, NULL); in test_panic_nopause()
37 qpci_memread(dev, bar, 0, &val, sizeof(val)); in test_panic_nopause()
41 qpci_memwrite(dev, bar, 0, &val, sizeof(val)); in test_panic_nopause()
66 dev = qpci_device_find(pcibus, QPCI_DEVFN(0x4, 0x0)); in test_panic()
68 bar = qpci_iomap(dev, 0, NULL); in test_panic()
70 qpci_memread(dev, bar, 0, &val, sizeof(val)); in test_panic()
74 qpci_memwrite(dev, bar, 0, &val, sizeof(val)); in test_panic()
99 dev = qpci_device_find(pcibus, QPCI_DEVFN(0x4, 0x0)); in test_pvshutdown()
101 bar = qpci_iomap(dev, 0, NULL); in test_pvshutdown()
[all …]
/qemu/pc-bios/keymaps/
H A Dsv1 map 0x0000041d
3 Shift_R 0x36
4 Shift_L 0x2a
6 Alt_R 0xb8
7 Mode_switch 0xb8
8 ISO_Level3_Shift 0xb8
9 Alt_L 0x38
11 Control_R 0x9d
12 Control_L 0x1d
16 Super_R 0xdc
[all …]
/qemu/docs/specs/
H A Dppc-spapr-numa.rst19 bit 0 of byte 5 of the ibm,architecture-vec-5 property. The format with
20 bit 0 equal to zero is deprecated. The current format, with the bit 0
53 The definition of its elements also varies with the value of bit 0 of byte 5
54 of the ibm,architecture-vec-5 property. The format with bit 0 equal to zero
69 * ibm,associativity-reference-points = {0x3, 0x2, 0x1}
71 The first NUMA level (0x3) is interpreted as the third element of each
81 * ibm,associativity-reference-points = {0x3, 0x2, 0x1}
85 First NUMA level (0x3) => associativity[2] = C1
86 Second NUMA level (0x2) => associativity[1] = S1
87 Third NUMA level (0x1) => associativity[0] = MOD1
[all …]
/qemu/tests/tcg/aarch64/system/
H A Dboot.S16 #define semihosting_call hlt 0xf000
17 #define SYS_WRITEC 0x03 /* character to debug channel */
18 #define SYS_WRITE0 0x04 /* string to debug channel */
19 #define SYS_GET_CMDLINE 0x15 /* get command line */
20 #define SYS_EXIT 0x18
123 subs w11, w11, #'0'
169 orr x0, x0, #(1 << 0) /* NS = 1: Non-secure state */
178 cbz x0, el2_not_present /* If field is 0 no EL2 */
182 mov x0, #0x3c9 /* DAIF bits and EL2h mode (9) */
201 mov x0, #0x3c5 /* DAIF bits and EL1h mode (5) */
[all …]

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