41 #define IOMMU_CTRL              0x0
47 #define IOMMU_BASE              0x8
48 #define IOMMU_FLUSH             0x10
54 #define IOMMU_TTE_PHYS_MASK_8K  0x1ffffffe000ULL
55 #define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL
57 #define IOMMU_TSB_8K_OFFSET_MASK_8M    0x00000000007fe000ULL
58 #define IOMMU_TSB_8K_OFFSET_MASK_16M   0x0000000000ffe000ULL
59 #define IOMMU_TSB_8K_OFFSET_MASK_32M   0x0000000001ffe000ULL
60 #define IOMMU_TSB_8K_OFFSET_MASK_64M   0x0000000003ffe000ULL
61 #define IOMMU_TSB_8K_OFFSET_MASK_128M  0x0000000007ffe000ULL
62 #define IOMMU_TSB_8K_OFFSET_MASK_256M  0x000000000fffe000ULL
63 #define IOMMU_TSB_8K_OFFSET_MASK_512M  0x000000001fffe000ULL
64 #define IOMMU_TSB_8K_OFFSET_MASK_1G    0x000000003fffe000ULL
66 #define IOMMU_TSB_64K_OFFSET_MASK_64M  0x0000000003ff0000ULL
67 #define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL
68 #define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL
69 #define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL
70 #define IOMMU_TSB_64K_OFFSET_MASK_1G   0x000000003fff0000ULL
71 #define IOMMU_TSB_64K_OFFSET_MASK_2G   0x000000007fff0000ULL
85         .iova = 0,  in sun4u_translate_iommu()
86         .translated_addr = 0,  in sun4u_translate_iommu()
87         .addr_mask = ~(hwaddr)0,  in sun4u_translate_iommu()
102     tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7;  in sun4u_translate_iommu()
107         case 0:  in sun4u_translate_iommu()
132         case 0:  in sun4u_translate_iommu()
202             is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL;  in iommu_mem_write()
208     case IOMMU_CTRL + 0x4:  in iommu_mem_write()
209         is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL;  in iommu_mem_write()
210         is->regs[IOMMU_CTRL >> 3] |= val & 0xffffffffULL;  in iommu_mem_write()
214             is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL;  in iommu_mem_write()
220     case IOMMU_BASE + 0x4:  in iommu_mem_write()
221         is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL;  in iommu_mem_write()
222         is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL;  in iommu_mem_write()
225     case IOMMU_FLUSH + 0x4:  in iommu_mem_write()
230                   "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",  in iommu_mem_write()
249     case IOMMU_CTRL + 0x4:  in iommu_mem_read()
250         val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL;  in iommu_mem_read()
259     case IOMMU_BASE + 0x4:  in iommu_mem_read()
260         val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL;  in iommu_mem_read()
263     case IOMMU_FLUSH + 0x4:  in iommu_mem_read()
264         val = 0;  in iommu_mem_read()
269                       "reg 0x%" HWADDR_PRIx " size 0x%x\n",  in iommu_mem_read()
271         val = 0;  in iommu_mem_read()
290     memset(s->regs, 0, IOMMU_NREGS * sizeof(uint64_t));  in iommu_reset()