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/linux-5.10/arch/m68k/include/asm/
Dfbio.h13 #define FBTYPE_SUN1BW 0 /* mono */
58 #define FBIOGTYPE _IOR('F', 0, struct fbtype)
61 int index; /* first element (0 origin) */
124 #define FB_WID_SHARED_8 0
196 #define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
225 #define CG6_FBC 0x70000000
226 #define CG6_TEC 0x70001000
227 #define CG6_BTREGS 0x70002000
228 #define CG6_FHC 0x70004000
229 #define CG6_THC 0x70005000
[all …]
/linux-5.10/include/linux/
Dswitchtec.h16 #define SWITCHTEC_EVENT_OCCURRED BIT(0)
17 #define SWITCHTEC_EVENT_CLEAR BIT(0)
23 #define SWITCHTEC_DMA_MRPC_EN BIT(0)
25 #define MRPC_GAS_READ 0x29
26 #define MRPC_GAS_WRITE 0x87
27 #define MRPC_CMD_ID(x) ((x) & 0xffff)
30 SWITCHTEC_GAS_MRPC_OFFSET = 0x0000,
31 SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000,
32 SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800,
33 SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000,
[all …]
/linux-5.10/drivers/gpu/drm/amd/include/
Damd_shared.h35 AMD_ASIC_MASK = 0x0000ffffUL,
36 AMD_FLAGS_MASK = 0xffff0000UL,
37 AMD_IS_MOBILITY = 0x00010000UL,
38 AMD_IS_APU = 0x00020000UL,
39 AMD_IS_PX = 0x00040000UL,
40 AMD_EXP_HW_SUPPORT = 0x00080000UL,
44 AMD_APU_IS_RAVEN = 0x00000001UL,
45 AMD_APU_IS_RAVEN2 = 0x00000002UL,
46 AMD_APU_IS_PICASSO = 0x00000004UL,
47 AMD_APU_IS_RENOIR = 0x00000008UL,
[all …]
/linux-5.10/arch/arm64/boot/dts/rockchip/
Drk3368.dtsi39 #address-cells = <0x2>;
40 #size-cells = <0x0>;
74 cpu_l0: cpu@0 {
77 reg = <0x0 0x0>;
85 reg = <0x0 0x1>;
93 reg = <0x0 0x2>;
101 reg = <0x0 0x3>;
109 reg = <0x0 0x100>;
117 reg = <0x0 0x101>;
125 reg = <0x0 0x102>;
[all …]
/linux-5.10/arch/arm/boot/dts/
Dsun9i-a80.dtsi65 #size-cells = <0>;
67 cpu0: cpu@0 {
73 reg = <0x0>;
82 reg = <0x1>;
91 reg = <0x2>;
100 reg = <0x3>;
109 reg = <0x100>;
118 reg = <0x101>;
127 reg = <0x102>;
136 reg = <0x103>;
[all …]
Dsun8i-a83t.dtsi62 #size-cells = <0>;
64 cpu0: cpu@0 {
71 reg = <0>;
115 reg = <0x100>;
126 reg = <0x101>;
137 reg = <0x102>;
148 reg = <0x103>;
168 #clock-cells = <0>;
181 #clock-cells = <0>;
188 #clock-cells = <0>;
[all …]
/linux-5.10/drivers/net/ethernet/rdc/
Dr6040.c50 #define MCR0 0x00 /* Control register 0 */
51 #define MCR0_RCVEN 0x0002 /* Receive enable */
52 #define MCR0_PROMISC 0x0020 /* Promiscuous mode */
53 #define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
54 #define MCR0_XMTEN 0x1000 /* Transmission enable */
55 #define MCR0_FD 0x8000 /* Full/Half duplex */
56 #define MCR1 0x04 /* Control register 1 */
57 #define MAC_RST 0x0001 /* Reset the MAC */
58 #define MBCR 0x08 /* Bus control */
59 #define MT_ICR 0x0C /* TX interrupt control */
[all …]
/linux-5.10/drivers/net/wireless/broadcom/b43legacy/
Dphy.c33 0x4D, 0x4C, 0x4B, 0x4A,
34 0x4A, 0x49, 0x48, 0x47,
35 0x47, 0x46, 0x45, 0x45,
36 0x44, 0x43, 0x42, 0x42,
37 0x41, 0x40, 0x3F, 0x3E,
38 0x3D, 0x3C, 0x3B, 0x3A,
39 0x39, 0x38, 0x37, 0x36,
40 0x35, 0x34, 0x32, 0x31,
41 0x30, 0x2F, 0x2D, 0x2C,
42 0x2B, 0x29, 0x28, 0x26,
[all …]
/linux-5.10/drivers/crypto/
Dhifn_795x.c34 #define ACRYPTO_OP_DECRYPT 0
39 #define ACRYPTO_MODE_ECB 0
44 #define ACRYPTO_TYPE_AES_128 0
50 #define PCI_VENDOR_ID_HIFN 0x13A3
51 #define PCI_DEVICE_ID_HIFN_7955 0x0020
52 #define PCI_DEVICE_ID_HIFN_7956 0x001d
56 #define HIFN_BAR0_SIZE 0x1000
57 #define HIFN_BAR1_SIZE 0x2000
58 #define HIFN_BAR2_SIZE 0x8000
62 #define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */
[all …]
/linux-5.10/arch/powerpc/boot/
Drs6000.h70 #define RS6K_AOUTHDR_OMAGIC 0x0107 /* old: text & data writeable */
71 #define RS6K_AOUTHDR_NMAGIC 0x0108 /* new: text r/o, data r/w */
72 #define RS6K_AOUTHDR_ZMAGIC 0x010B /* paged: text r/o, both page-aligned */
104 #define STYP_LOADER 0x1000
107 #define STYP_DEBUG 0x2000
111 #define STYP_OVRFLO 0x8000
117 * grouping will have l_lnno = 0 and in place of physical address will be the
122 char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/
221 #define DBXMASK 0x80 /* for dbx storage mask */
/linux-5.10/arch/arm64/boot/dts/renesas/
Dr8a77951.dtsi31 * The external audio clocks are configured as 0 Hz fixed frequency
37 #clock-cells = <0>;
38 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #clock-cells = <0>;
50 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
117 #size-cells = <0>;
[all …]
/linux-5.10/drivers/net/ethernet/microchip/
Denc28j60_hw.h15 * - Register address (bits 0-4)
19 #define ADDR_MASK 0x1F
20 #define BANK_MASK 0x60
21 #define SPRD_MASK 0x80
23 #define EIE 0x1B
24 #define EIR 0x1C
25 #define ESTAT 0x1D
26 #define ECON2 0x1E
27 #define ECON1 0x1F
28 /* Bank 0 registers */
[all …]
/linux-5.10/arch/powerpc/boot/dts/
Dsbc8548-post.dtsi15 ranges = <0x00000000 0xe0000000 0x00100000>;
16 bus-frequency = <0>;
19 ecm-law@0 {
21 reg = <0x0 0x1000>;
27 reg = <0x1000 0x1000>;
34 reg = <0x2000 0x1000>;
36 interrupts = <0x12 0x2>;
41 reg = <0x20000 0x1000>;
42 cache-line-size = <0x20>; // 32 bytes
43 cache-size = <0x80000>; // L2, 512K
[all …]
Dbamboo.dts21 dcr-parent = <&{/cpus/cpu@0}>;
34 #size-cells = <0>;
36 cpu@0 {
39 reg = <0x00000000>;
40 clock-frequency = <0>; /* Filled in by zImage */
41 timebase-frequency = <0>; /* Filled in by zImage */
53 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
59 cell-index = <0>;
60 dcr-reg = <0x0c0 0x009>;
61 #address-cells = <0>;
[all …]
Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
38 reg = <0x00000000 0x04000000>; // 64MB
45 ranges = <0 0xf0000000 0x0000c000>;
[all …]
Dsocrates.dts27 #size-cells = <0>;
29 PowerPC,8544@0 {
31 reg = <0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x00000000 0xe0000000 0x00100000>;
[all …]
Dtqm8540.dts27 #size-cells = <0>;
29 PowerPC,8540@0 {
31 reg = <0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x10000000>;
52 ranges = <0x0 0xe0000000 0x100000>;
53 bus-frequency = <0>;
56 ecm-law@0 {
[all …]
Dac14xx.dts25 PowerPC,5121@0 {
33 reg = <0x00000000 0x10000000>; /* 256MB at 0 */
41 ranges = <0x0 0x0 0xfc000000 0x04000000 /* CS0: NOR flash */
42 0x1 0x0 0xe0000000 0x00010000 /* CS1: FRAM */
43 0x2 0x0 0xe0100000 0x00080000 /* CS2: asi1 */
44 0x3 0x0 0xe0300000 0x00020000 /* CS3: comm */
45 0x5 0x0 0xe0400000 0x00010000 /* CS5: safety */
46 0x6 0x0 0xe0200000 0x00080000>; /* CS6: asi2 */
48 flash@0,0 {
50 reg = <0 0x00000000 0x04000000>;
[all …]
/linux-5.10/drivers/media/i2c/s5c73m3/
Ds5c73m3.h44 #define AHB_MSB_ADDR_PTR 0xfcfc
45 #define REG_CMDWR_ADDRH 0x0050
46 #define REG_CMDWR_ADDRL 0x0054
47 #define REG_CMDRD_ADDRH 0x0058
48 #define REG_CMDRD_ADDRL 0x005c
49 #define REG_CMDBUF_ADDR 0x0f14
51 #define REG_I2C_SEQ_STATUS S5C73M3_REG(0x0009, 0x59A6)
52 #define SEQ_END_PLL (1<<0x0)
53 #define SEQ_END_SENSOR (1<<0x1)
54 #define SEQ_END_GPIO (1<<0x2)
[all …]
/linux-5.10/drivers/scsi/
Daha152x.h16 #define SCSISEQ (HOSTIOPORT0+0x00) /* SCSI sequence control */
17 #define SXFRCTL0 (HOSTIOPORT0+0x01) /* SCSI transfer control 0 */
18 #define SXFRCTL1 (HOSTIOPORT0+0x02) /* SCSI transfer control 1 */
19 #define SCSISIG (HOSTIOPORT0+0x03) /* SCSI signal in/out */
20 #define SCSIRATE (HOSTIOPORT0+0x04) /* SCSI rate control */
21 #define SELID (HOSTIOPORT0+0x05) /* selection/reselection ID */
23 #define SCSIDAT (HOSTIOPORT0+0x06) /* SCSI latched data */
24 #define SCSIBUS (HOSTIOPORT0+0x07) /* SCSI data bus */
25 #define STCNT0 (HOSTIOPORT0+0x08) /* SCSI transfer count 0 */
26 #define STCNT1 (HOSTIOPORT0+0x09) /* SCSI transfer count 1 */
[all …]
/linux-5.10/drivers/gpu/drm/shmobile/
Dshmob_drm_regs.h19 #define LDDCKPAT1R 0x400
20 #define LDDCKPAT2R 0x404
21 #define LDDCKR 0x410
22 #define LDDCKR_ICKSEL_BUS (0 << 16)
28 #define LDDCKSTPR 0x414
30 #define LDDCKSTPR_DCKSTP (1 << 0)
31 #define LDMT1R 0x418
40 #define LDMT1R_MIFTYP_RGB8 (0x0 << 0)
41 #define LDMT1R_MIFTYP_RGB9 (0x4 << 0)
42 #define LDMT1R_MIFTYP_RGB12A (0x5 << 0)
[all …]
/linux-5.10/arch/powerpc/include/asm/
Dmpc52xx_psc.h35 #define MPC52xx_PSC_SR_UNEX_RX 0x0001
36 #define MPC52xx_PSC_SR_DATA_VAL 0x0002
37 #define MPC52xx_PSC_SR_DATA_OVR 0x0004
38 #define MPC52xx_PSC_SR_CMDSEND 0x0008
39 #define MPC52xx_PSC_SR_CDE 0x0080
40 #define MPC52xx_PSC_SR_RXRDY 0x0100
41 #define MPC52xx_PSC_SR_RXFULL 0x0200
42 #define MPC52xx_PSC_SR_TXRDY 0x0400
43 #define MPC52xx_PSC_SR_TXEMP 0x0800
44 #define MPC52xx_PSC_SR_OE 0x1000
[all …]
/linux-5.10/drivers/net/ethernet/apm/xgene/
Dxgene_enet_hw.h40 #define CSR_RING_ID 0x0008
44 #define CSR_RING_ID_BUF 0x000c
45 #define CSR_PBM_COAL 0x0014
46 #define CSR_PBM_CTICK0 0x0018
47 #define CSR_PBM_CTICK1 0x001c
48 #define CSR_PBM_CTICK2 0x0020
49 #define CSR_PBM_CTICK3 0x0024
50 #define CSR_THRESHOLD0_SET1 0x0030
51 #define CSR_THRESHOLD1_SET1 0x0034
52 #define CSR_RING_NE_INT_MODE 0x017c
[all …]
/linux-5.10/drivers/net/ethernet/intel/e1000e/
Dich8lan.h7 #define ICH_FLASH_GFPREG 0x0000
8 #define ICH_FLASH_HSFSTS 0x0004
9 #define ICH_FLASH_HSFCTL 0x0006
10 #define ICH_FLASH_FADDR 0x0008
11 #define ICH_FLASH_FDATA0 0x0010
12 #define ICH_FLASH_PR0 0x0074
18 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
21 #define ICH_CYCLE_READ 0
25 #define FLASH_GFPREG_BASE_MASK 0x1FFF
33 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
[all …]
/linux-5.10/arch/sparc/include/asm/
Dbbc.h17 #define BBC_AID 0x00 /* [B] Agent ID */
18 #define BBC_DEVP 0x01 /* [B] Device Present */
19 #define BBC_ARB 0x02 /* [B] Arbitration */
20 #define BBC_QUIESCE 0x03 /* [B] Quiesce */
21 #define BBC_WDACTION 0x04 /* [B] Watchdog Action */
22 #define BBC_SPG 0x06 /* [B] Soft POR Gen */
23 #define BBC_SXG 0x07 /* [B] Soft XIR Gen */
24 #define BBC_PSRC 0x08 /* [W] POR Source */
25 #define BBC_XSRC 0x0c /* [B] XIR Source */
26 #define BBC_CSC 0x0d /* [B] Clock Synthesizers Control*/
[all …]

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