boot/dts/bamboo.dts

21 	dcr-parent = <&{/cpus/cpu@0}>;
34 		#size-cells = <0>;
36 		cpu@0 {
39 			reg = <0x00000000>;
40 			clock-frequency = <0>; /* Filled in by zImage */
41 			timebase-frequency = <0>; /* Filled in by zImage */
53 		reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by zImage */
59 		cell-index = <0>;
60 		dcr-reg = <0x0c0 0x009>;
61 		#address-cells = <0>;
62 		#size-cells = <0>;
70 		dcr-reg = <0x0d0 0x009>;
71 		#address-cells = <0>;
72 		#size-cells = <0>;
74 		interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
80 		dcr-reg = <0x00e 0x002>;
85 		dcr-reg = <0x00c 0x002>;
93 		clock-frequency = <0>; /* Filled in by zImage */
97 			dcr-reg = <0x010 0x002>;
102 			dcr-reg = <0x100 0x027>;
107 			dcr-reg = <0x180 0x062>;
111 			interrupts = <0x0 0x1 0x2 0x3 0x4>;
113 			#address-cells = <0>;
114 			#size-cells = <0>;
115 			interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
116 					/*RXEOB*/ 0x1 &UIC0 0xb 0x4
117 					/*SERR*/  0x2 &UIC1 0x0 0x4
118 					/*TXDE*/  0x3 &UIC1 0x1 0x4
119 					/*RXDE*/  0x4 &UIC1 0x2 0x4>;
129 		  	ranges = <0x00000000 0x00000000 0x00000000 0x80000000
130 			          0x80000000 0x00000000 0x80000000 0x80000000>;
132 		  	interrupts = <0x7 0x4>;
133 		  	clock-frequency = <0>; /* Filled in by zImage */
137 				dcr-reg = <0x012 0x002>;
140 				clock-frequency = <0>; /* Filled in by zImage */
141 				interrupts = <0x5 0x1>;
148 		   		reg = <0xef600300 0x00000008>;
149 		   		virtual-reg = <0xef600300>;
150 		   		clock-frequency = <0>; /* Filled in by zImage */
153 		   		interrupts = <0x0 0x4>;
159 		   		reg = <0xef600400 0x00000008>;
160 		   		virtual-reg = <0xef600400>;
161 		   		clock-frequency = <0>;
162 		   		current-speed = <0>;
164 		   		interrupts = <0x1 0x4>;
170 		   		reg = <0xef600500 0x00000008>;
171 		   		virtual-reg = <0xef600500>;
172 		   		clock-frequency = <0>;
173 		   		current-speed = <0>;
175 		   		interrupts = <0x3 0x4>;
181 		   		reg = <0xef600600 0x00000008>;
182 		   		virtual-reg = <0xef600600>;
183 		   		clock-frequency = <0>;
184 		   		current-speed = <0>;
186 		   		interrupts = <0x4 0x4>;
191 				reg = <0xef600700 0x00000014>;
193 				interrupts = <0x2 0x4>;
198 				reg = <0xef600800 0x00000014>;
200 				interrupts = <0x7 0x4>;
205 				reg = <0xef600d00 0x0000000c>;
212 				interrupts = <0x1c 0x4 0x1d 0x4>;
213 				reg = <0xef600e00 0x00000070>;
216 				mal-tx-channel = <0 1>;
217 				mal-rx-channel = <0>;
218 				cell-index = <0>;
223 				phy-map = <0x00000000>;
225 				zmii-channel = <0>;
232 				interrupts = <0x1e 0x4 0x1f 0x4>;
233 				reg = <0xef600f00 0x00000070>;
243 				phy-map = <0x00000000>;
250 				reg = <0xef601000 0x00000080>;
251 				interrupts = <0x8 0x1 0x9 0x1>;
263 			reg = <0x00000000 0xeec00000 0x00000008	/* Config space access */
264 			       0x00000000 0xeed00000 0x00000004	/* IACK */
265 			       0x00000000 0xeed00000 0x00000004	/* Special cycle */
266 			       0x00000000 0xef400000 0x00000040>;	/* Internal registers */
274 			ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000 0x00000000 0x20000000
275 				  0x02000000 0x00000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00100000
276 				  0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
278 			/* Inbound 2GB range starting at 0 */
279 			dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
282 			interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
285 				0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
288 				0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8
291 				0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8
294 				0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8